89 lines
3.2 KiB
LLVM
89 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=GFX6 %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s
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; Test for compilation only. This generated an invalid machine instruction
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; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both
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; of which were in SGPRs.
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define amdgpu_vs float @main(i32 %v) {
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; GFX6-LABEL: main:
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; GFX6: ; %bb.0: ; %main_body
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; GFX6-NEXT: s_cbranch_scc1 .LBB0_2
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; GFX6-NEXT: ; %bb.1: ; %IF57
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; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GFX6-NEXT: .LBB0_2: ; %ENDIF56
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; GFX6-NEXT: s_buffer_load_dword s0, s[0:3], 0xf0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_cmp_eq_u32 s0, 0
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; GFX6-NEXT: s_cbranch_scc1 .LBB0_4
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; GFX6-NEXT: ; %bb.3: ; %IF60
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; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GFX6-NEXT: .LBB0_4: ; %ENDIF59
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; GFX6-NEXT: s_buffer_load_dword s0, s[0:3], 0xf4
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_cmp_eq_u32 s0, 0
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; GFX6-NEXT: s_cbranch_scc0 .LBB0_6
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; GFX6-NEXT: ; %bb.5: ; %ENDIF62
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; GFX6-NEXT: s_branch .LBB0_7
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; GFX6-NEXT: .LBB0_6: ; %IF63
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; GFX6-NEXT: .LBB0_7:
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;
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; GFX8-LABEL: main:
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; GFX8: ; %bb.0: ; %main_body
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; GFX8-NEXT: s_cbranch_scc1 .LBB0_2
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; GFX8-NEXT: ; %bb.1: ; %IF57
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; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GFX8-NEXT: .LBB0_2: ; %ENDIF56
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; GFX8-NEXT: s_buffer_load_dword s0, s[0:3], 0x3c0
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: s_cmp_eq_u32 s0, 0
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; GFX8-NEXT: s_cbranch_scc1 .LBB0_4
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; GFX8-NEXT: ; %bb.3: ; %IF60
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; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GFX8-NEXT: .LBB0_4: ; %ENDIF59
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; GFX8-NEXT: s_buffer_load_dword s0, s[0:3], 0x3d0
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: s_cmp_eq_u32 s0, 0
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; GFX8-NEXT: s_cbranch_scc0 .LBB0_6
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; GFX8-NEXT: ; %bb.5: ; %ENDIF62
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; GFX8-NEXT: s_branch .LBB0_7
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; GFX8-NEXT: .LBB0_6: ; %IF63
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; GFX8-NEXT: .LBB0_7:
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main_body:
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%d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 960, i32 0)
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%d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 976, i32 0)
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br i1 poison, label %ENDIF56, label %IF57
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IF57: ; preds = %ENDIF
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%v.1 = mul i32 %v, 2
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br label %ENDIF56
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ENDIF56: ; preds = %IF57, %ENDIF
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%v.2 = phi i32 [ %v, %main_body ], [ %v.1, %IF57 ]
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%d1.i = bitcast float %d1 to i32
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%cc1 = icmp eq i32 %d1.i, 0
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br i1 %cc1, label %ENDIF59, label %IF60
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IF60: ; preds = %ENDIF56
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%v.3 = mul i32 %v.2, 2
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br label %ENDIF59
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ENDIF59: ; preds = %IF60, %ENDIF56
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%v.4 = phi i32 [ %v.2, %ENDIF56 ], [ %v.3, %IF60 ]
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%d2.i = bitcast float %d2 to i32
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%cc2 = icmp eq i32 %d2.i, 0
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br i1 %cc2, label %ENDIF62, label %IF63
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IF63: ; preds = %ENDIF59
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unreachable
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ENDIF62: ; preds = %ENDIF59
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%r = bitcast i32 %v.4 to float
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ret float %r
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}
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declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { readnone }
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