fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
99 lines
4.1 KiB
LLVM
99 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
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define amdgpu_kernel void @private_load_maybe_divergent(ptr addrspace(4) %k, ptr %flat) {
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; GCN-LABEL: private_load_maybe_divergent:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_add_i32 s12, s12, s17
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; GCN-NEXT: s_mov_b64 s[22:23], s[2:3]
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; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
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; GCN-NEXT: s_mov_b64 s[20:21], s[0:1]
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; GCN-NEXT: s_add_u32 s20, s20, s17
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; GCN-NEXT: s_addc_u32 s21, s21, 0
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; GCN-NEXT: buffer_load_dword v0, v0, s[20:23], 0 offen glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v2, s1
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; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; GCN-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
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; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v0
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; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
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; GCN-NEXT: flat_load_dword v0, v[0:1]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: flat_store_dword v[0:1], v0
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; GCN-NEXT: s_endpgm
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%load = load volatile i32, ptr addrspace(5) poison, align 4
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%gep = getelementptr inbounds i32, ptr addrspace(4) %k, i32 %load
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%maybe.not.uniform.load = load i32, ptr addrspace(4) %gep, align 4
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store i32 %maybe.not.uniform.load, ptr addrspace(1) poison
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ret void
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}
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define amdgpu_kernel void @flat_load_maybe_divergent(ptr addrspace(4) %k, ptr %flat) {
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; GCN-LABEL: flat_load_maybe_divergent:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; GCN-NEXT: s_add_i32 s12, s12, s17
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; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
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; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s2
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; GCN-NEXT: v_mov_b32_e32 v1, s3
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; GCN-NEXT: flat_load_dword v0, v[0:1]
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; GCN-NEXT: v_mov_b32_e32 v2, s1
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; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; GCN-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
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; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v0
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; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
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; GCN-NEXT: flat_load_dword v0, v[0:1]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: flat_store_dword v[0:1], v0
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; GCN-NEXT: s_endpgm
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%load = load i32, ptr %flat, align 4
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%gep = getelementptr inbounds i32, ptr addrspace(4) %k, i32 %load
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%maybe.not.uniform.load = load i32, ptr addrspace(4) %gep, align 4
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store i32 %maybe.not.uniform.load, ptr addrspace(1) poison
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ret void
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}
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; This decomposes into a sequence of divergent sub carries. The first
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; subs in the sequence are divergent from the value inputs, but the
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; last values are divergent due to the carry in glue (such that
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; divergence needs to propagate through glue if there are any non-void
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; outputs)
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define <2 x i128> @wide_carry_divergence_error(i128 %arg) {
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; GCN-LABEL: wide_carry_divergence_error:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_ffbh_u32_e32 v0, v0
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; GCN-NEXT: v_ffbh_u32_e32 v4, v2
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; GCN-NEXT: v_add_u32_e64 v0, s[4:5], v0, 32 clamp
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; GCN-NEXT: v_ffbh_u32_e32 v1, v1
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; GCN-NEXT: v_add_u32_e32 v4, vcc, 32, v4
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; GCN-NEXT: v_min3_u32 v0, v0, v1, 64
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; GCN-NEXT: v_add_u32_e32 v0, vcc, 64, v0
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; GCN-NEXT: v_ffbh_u32_e32 v5, v3
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; GCN-NEXT: v_addc_u32_e64 v1, s[4:5], 0, 0, vcc
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; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
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; GCN-NEXT: v_min_u32_e32 v4, v4, v5
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; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
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; GCN-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
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; GCN-NEXT: v_sub_u32_e32 v0, vcc, 0, v0
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; GCN-NEXT: v_mov_b32_e32 v3, 0
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; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
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; GCN-NEXT: v_subb_u32_e32 v2, vcc, 0, v3, vcc
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; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
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; GCN-NEXT: v_mov_b32_e32 v4, 0
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; GCN-NEXT: v_mov_b32_e32 v5, 0
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; GCN-NEXT: v_mov_b32_e32 v6, 0
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; GCN-NEXT: v_mov_b32_e32 v7, 0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%i = call i128 @llvm.ctlz.i128(i128 %arg, i1 false)
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%i1 = sub i128 0, %i
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%i2 = insertelement <2 x i128> zeroinitializer, i128 %i1, i64 0
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ret <2 x i128> %i2
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}
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