fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
85 lines
2.7 KiB
LLVM
85 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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define amdgpu_kernel void @eq_t(float %x) {
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; GCN-LABEL: eq_t:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s0, s[4:5], 0x24
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, 1.0
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; GCN-NEXT: v_cndmask_b32_e64 v0, 2.0, 4.0, s[0:1]
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; GCN-NEXT: flat_store_dword v[0:1], v0
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; GCN-NEXT: s_endpgm
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%c1 = fcmp olt float %x, 1.0
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%s1 = select i1 %c1, i32 56789, i32 1
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%c2 = icmp eq i32 %s1, 56789
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%s2 = select i1 %c2, float 4.0, float 2.0
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store float %s2, ptr poison, align 4
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ret void
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}
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define amdgpu_kernel void @ne_t(float %x) {
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; GCN-LABEL: ne_t:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s0, s[4:5], 0x24
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_cmp_nlt_f32_e64 s[0:1], s0, 1.0
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; GCN-NEXT: v_cndmask_b32_e64 v0, 2.0, 4.0, s[0:1]
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; GCN-NEXT: flat_store_dword v[0:1], v0
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; GCN-NEXT: s_endpgm
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%c1 = fcmp olt float %x, 1.0
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%s1 = select i1 %c1, i32 56789, i32 1
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%c2 = icmp ne i32 %s1, 56789
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%s2 = select i1 %c2, float 4.0, float 2.0
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store float %s2, ptr poison, align 4
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ret void
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}
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define amdgpu_kernel void @eq_f(float %x) {
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; GCN-LABEL: eq_f:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s0, s[4:5], 0x24
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_cmp_nlt_f32_e64 s[0:1], s0, 1.0
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; GCN-NEXT: v_cndmask_b32_e64 v0, 2.0, 4.0, s[0:1]
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; GCN-NEXT: flat_store_dword v[0:1], v0
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; GCN-NEXT: s_endpgm
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%c1 = fcmp olt float %x, 1.0
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%s1 = select i1 %c1, i32 1, i32 56789
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%c2 = icmp eq i32 %s1, 56789
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%s2 = select i1 %c2, float 4.0, float 2.0
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store float %s2, ptr poison, align 4
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ret void
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}
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define amdgpu_kernel void @ne_f(float %x) {
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; GCN-LABEL: ne_f:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s0, s[4:5], 0x24
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, 1.0
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; GCN-NEXT: v_cndmask_b32_e64 v0, 2.0, 4.0, s[0:1]
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; GCN-NEXT: flat_store_dword v[0:1], v0
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; GCN-NEXT: s_endpgm
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%c1 = fcmp olt float %x, 1.0
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%s1 = select i1 %c1, i32 1, i32 56789
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%c2 = icmp ne i32 %s1, 56789
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%s2 = select i1 %c2, float 4.0, float 2.0
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store float %s2, ptr poison, align 4
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ret void
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}
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define amdgpu_kernel void @different_constants(float %x) {
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; GCN-LABEL: different_constants:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_mov_b32_e32 v0, 2.0
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; GCN-NEXT: flat_store_dword v[0:1], v0
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; GCN-NEXT: s_endpgm
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%c1 = fcmp olt float %x, 1.0
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%s1 = select i1 %c1, i32 56789, i32 1
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%c2 = icmp eq i32 %s1, 5678
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%s2 = select i1 %c2, float 4.0, float 2.0
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store float %s2, ptr poison, align 4
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ret void
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}
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