9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
34 lines
1.1 KiB
LLVM
34 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx908 < %s | FileCheck %s
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define void @wombat(i1 %cond, ptr addrspace(5) %addr) {
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; CHECK-LABEL: wombat:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: buffer_load_ubyte v2, v1, s[0:3], 0 offen
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; CHECK-NEXT: s_cbranch_execz .LBB0_2
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; CHECK-NEXT: ; %bb.1: ; %then
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: .LBB0_2: ; %end
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; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: buffer_store_byte v2, v1, s[0:3], 0 offen
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%load = load <1 x i8>, ptr addrspace(5) %addr, align 1
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br i1 %cond, label %then, label %end
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then:
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br label %end
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end:
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%phi_value = phi <1 x i8> [%load, %entry], [zeroinitializer, %then]
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store <1 x i8> %phi_value, ptr addrspace(5) %addr, align 1
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ret void
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}
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