86627149f6
Any SGPR read by a VALU can potentially obscure SALU writes to the same register. Insert s_wait_alu instructions to mitigate the hazard on affected paths. Compute a global cache of SGPRs with any VALU reads and use this to avoid inserting mitigation for SGPRs never accessed by VALUs. To avoid excessive search when compile time is priority implement secondary mode where all SALU writes are mitigated. Co-authored-by: Shilei Tian <shilei.tian@amd.com>
24 lines
789 B
LLVM
24 lines
789 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=gfx1201 %s -o - | FileCheck %s
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define amdgpu_kernel void @foo() {
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; CHECK-LABEL: foo:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_mov_b64 s[0:1], src_shared_base
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; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s1
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; CHECK-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, v0
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; CHECK-NEXT: flat_store_b64 v[0:1], v[2:3]
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; CHECK-NEXT: s_endpgm
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entry:
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br label %bb1
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bb0:
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br label %bb1
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bb1:
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%dst = phi ptr [ null, %bb0 ], [ addrspacecast (ptr addrspace(3) null to ptr), %entry ]
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store i64 0, ptr %dst, align 16
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ret void
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}
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