3ba4092c06
For register constraints that require specific register ranges, the width of the range should match the type of the associated parameter/return value. With this PR, we error out when that is not the case. Previously, these cases would hit assertions or llvm_unreachables. The handling of register constraints that require only a single register remains more lenient to allow narrower non-vector types for the associated IR values. For example, constraining an i16 or i8 value to a 32-bit register is still allowed. Fixes #101190. --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
163 lines
5.2 KiB
LLVM
163 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=CHECK %s
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; Allow single registers that are too wide for the IR type:
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define i16 @inline_asm_i16_in_v_def() {
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; CHECK-LABEL: inline_asm_i16_in_v_def:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def v8
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_and_b32_e32 v0, v8, v0
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%phys = call i16 asm sideeffect "; def $0", "={v8}"()
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%virt = call i16 asm sideeffect "; def $0", "=v"()
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%r = and i16 %phys, %virt
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ret i16 %r
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}
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define void @inline_asm_i16_in_v_use(i16 %val) {
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; CHECK-LABEL: inline_asm_i16_in_v_use:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v8, 0xffff, v0
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v8
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v8
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "{v8}"(i16 %val)
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call void asm sideeffect "; use $0", "v"(i16 %val)
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ret void
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}
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define i16 @inline_asm_i16_in_s_def() {
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; CHECK-LABEL: inline_asm_i16_in_s_def:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s8
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s4
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_and_b32 s4, s8, s4
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%phys = call i16 asm sideeffect "; def $0", "={s8}"()
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%virt = call i16 asm sideeffect "; def $0", "=s"()
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%r = and i16 %phys, %virt
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ret i16 %r
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}
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define i8 @inline_asm_i8_in_v_def() {
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; CHECK-LABEL: inline_asm_i8_in_v_def:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def v8
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_mov_b32_e32 v0, v8
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%phys = call i8 asm sideeffect "; def $0", "={v8}"()
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; %virt = call i8 asm sideeffect "; def $0", "=v"() ; currently fails
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; %r = and i8 %phys, %virt
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; ret i8 %r
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ret i8 %phys
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}
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; currently broken, v8 should be set to v0 & 0xFF
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define void @inline_asm_i8_in_v_use(i8 %val) {
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; CHECK-LABEL: inline_asm_i8_in_v_use:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v8, v0
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v8
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "{v8}"(i8 %val)
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; call void asm sideeffect "; use $0", "v"(i8 %val) ; currently fails
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ret void
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}
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define i8 @inline_asm_i8_in_sphys_def() {
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; CHECK-LABEL: inline_asm_i8_in_sphys_def:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s8
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_mov_b32_e32 v0, s8
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%phys = call i8 asm sideeffect "; def $0", "={s8}"()
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; %virt = call i8 asm sideeffect "; def $0", "=s"() ; currently fails
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; %r = and i8 %phys, %virt
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; ret i8 %r
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ret i8 %phys
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}
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; Single registers for vector types that fit are fine.
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define void @inline_asm_2xi16_in_v_use(<2 x i16> %val) {
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; CHECK-LABEL: inline_asm_2xi16_in_v_use:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v8, v0
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v8
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "; use $0", "{v8}"(<2 x i16> %val)
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call void asm sideeffect "; use $0", "v"(<2 x i16> %val)
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ret void
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}
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define <2 x i16> @inline_asm_2xi16_in_v_def() {
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; CHECK-LABEL: inline_asm_2xi16_in_v_def:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def v8
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_and_b32_e32 v0, v8, v0
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%phys = call <2 x i16> asm sideeffect "; def $0", "={v8}"()
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%virt = call <2 x i16> asm sideeffect "; def $0", "=v"()
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%r = and <2 x i16> %phys, %virt
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ret <2 x i16> %r
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}
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define <2 x i16> @inline_asm_2xi16_in_s_def() {
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; CHECK-LABEL: inline_asm_2xi16_in_s_def:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s8
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s4
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_and_b32 s4, s8, s4
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%phys = call <2 x i16> asm sideeffect "; def $0", "={s8}"()
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%virt = call <2 x i16> asm sideeffect "; def $0", "=s"()
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%r = and <2 x i16> %phys, %virt
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ret <2 x i16> %r
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}
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