5231736329
M0 can only be written to by the SALU, so `v_readfirstlane_b32 m0` is effectively useless. Represent this by restricting the dest RC of that instruction to `SReg_32_XM0` which excludes M0. There is a lot of test changes due to the register class changing, but most changes are trivial. In some cases, an extra register and `s_mov_b32` is needed. Fixes SWDEV-513269
135 lines
4.0 KiB
YAML
135 lines
4.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=early-machinelicm -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=early-machinelicm -o - %s | FileCheck -check-prefix=GCN %s
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---
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name: hoist_move
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: hoist_move
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: $exec = S_OR_B64 $exec, 1, implicit-def $scc
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; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.2
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: S_ENDPGM 0
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bb.0:
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S_BRANCH %bb.1
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bb.1:
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%0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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$exec = S_OR_B64 $exec, 1, implicit-def $scc
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S_CBRANCH_EXECNZ %bb.1, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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---
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name: no_hoist_cmp
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: no_hoist_cmp
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: S_BRANCH %bb.1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 1, 2, implicit $exec
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; GCN-NEXT: $exec = S_OR_B64 $exec, [[V_CMP_EQ_U32_e64_]], implicit-def $scc
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; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.2
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: S_ENDPGM 0
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bb.0:
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S_BRANCH %bb.1
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bb.1:
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%0:sreg_64 = V_CMP_EQ_U32_e64 1, 2, implicit $exec
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$exec = S_OR_B64 $exec, %0:sreg_64, implicit-def $scc
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S_CBRANCH_EXECNZ %bb.1, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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---
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name: allowable_hoist_cmp
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: allowable_hoist_cmp
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 1, 2, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: $exec = S_AND_B64 $exec, [[V_CMP_EQ_U32_e64_]], implicit-def $scc
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; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.2
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: S_ENDPGM 0
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bb.0:
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S_BRANCH %bb.1
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bb.1:
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%0:sreg_64 = V_CMP_EQ_U32_e64 1, 2, implicit $exec
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$exec = S_AND_B64 $exec, %0:sreg_64, implicit-def $scc
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S_CBRANCH_EXECNZ %bb.1, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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---
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name: no_hoist_readfirstlane
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: no_hoist_readfirstlane
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN-NEXT: S_BRANCH %bb.1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[DEF]], implicit $exec
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; GCN-NEXT: $exec = S_OR_B64 $exec, 1, implicit-def $scc
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; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.2
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: S_ENDPGM 0
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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S_BRANCH %bb.1
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bb.1:
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%1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0:vgpr_32, implicit $exec
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$exec = S_OR_B64 $exec, 1, implicit-def $scc
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S_CBRANCH_EXECNZ %bb.1, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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