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llvm-project/llvm/test/CodeGen/AMDGPU/live-interval-bug-in-rename-independent-subregs.mir
Pierre van Houtryve 5231736329
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851) 
M0 can only be written to by the SALU, so `v_readfirstlane_b32 m0` is
effectively useless. Represent this by restricting the dest RC of that
instruction to `SReg_32_XM0` which excludes M0.

There is a lot of test changes due to the register class changing, but
most changes are trivial. In some cases, an extra register and
`s_mov_b32` is needed.

Fixes SWDEV-513269
2025-02-26 13:14:03 +01:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -start-before=rename-independent-subregs -mattr=+wavefrontsize64 -stop-before=amdgpu-mark-last-scratch-load %s -o - | FileCheck -check-prefix=REG_ALLOC %s
# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -start-before=rename-independent-subregs -mattr=+wavefrontsize64 -stop-after=machine-cp %s -o - | FileCheck -check-prefix=DEAD_INST_DEL %s
---
name: _amdgpu_cs_main
tracksRegLiveness: true
body: |
; REG_ALLOC-LABEL: name: _amdgpu_cs_main
; REG_ALLOC: bb.0:
; REG_ALLOC-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; REG_ALLOC-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr10, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11
; REG_ALLOC-NEXT: {{ $}}
; REG_ALLOC-NEXT: renamable $vgpr5_vgpr6_vgpr7_vgpr8 = BUFFER_LOAD_DWORDX4_OFFEN renamable $vgpr3, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
; REG_ALLOC-NEXT: renamable $vgpr15_vgpr16_vgpr17_vgpr18 = BUFFER_LOAD_DWORDX4_OFFEN renamable $vgpr2, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
; REG_ALLOC-NEXT: renamable $vgpr11_vgpr12_vgpr13_vgpr14 = BUFFER_LOAD_DWORDX4_OFFEN renamable $vgpr0, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
; REG_ALLOC-NEXT: KILL killed renamable $vgpr2
; REG_ALLOC-NEXT: KILL killed renamable $vgpr0
; REG_ALLOC-NEXT: KILL killed renamable $vgpr3
; REG_ALLOC-NEXT: renamable $sgpr12 = V_READFIRSTLANE_B32 killed $vgpr5, implicit $exec
; REG_ALLOC-NEXT: renamable $vgpr4_vgpr5_vgpr6_vgpr7 = BUFFER_LOAD_DWORDX4_OFFEN killed renamable $vgpr4, killed renamable $sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
; REG_ALLOC-NEXT: renamable $sgpr13 = V_READFIRSTLANE_B32 killed $vgpr15, implicit $exec
; REG_ALLOC-NEXT: renamable $sgpr6_sgpr7 = V_CMP_NE_U32_e64 killed $vgpr1, 0, implicit $exec
; REG_ALLOC-NEXT: S_CMP_EQ_U64 killed renamable $sgpr12_sgpr13, killed renamable $sgpr2_sgpr3, implicit-def $scc
; REG_ALLOC-NEXT: renamable $sgpr1 = S_CSELECT_B32 1, 0, implicit $scc
; REG_ALLOC-NEXT: renamable $vgpr8 = IMPLICIT_DEF
; REG_ALLOC-NEXT: $exec = S_MOV_B64_term renamable $sgpr6_sgpr7
; REG_ALLOC-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
; REG_ALLOC-NEXT: S_BRANCH %bb.2
; REG_ALLOC-NEXT: {{ $}}
; REG_ALLOC-NEXT: bb.1:
; REG_ALLOC-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)
; REG_ALLOC-NEXT: liveins: $sgpr0, $vgpr8, $vgpr10, $sgpr4_sgpr5, $sgpr6_sgpr7, $vgpr11_vgpr12_vgpr13_vgpr14:0x0000000000000003, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7:0x0000000000000300
; REG_ALLOC-NEXT: {{ $}}
; REG_ALLOC-NEXT: renamable $sgpr2_sgpr3 = S_OR_SAVEEXEC_B64 killed renamable $sgpr6_sgpr7, implicit-def $exec, implicit-def $scc, implicit $exec
; REG_ALLOC-NEXT: $exec = S_XOR_B64_term $exec, renamable $sgpr2_sgpr3, implicit-def $scc
; REG_ALLOC-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
; REG_ALLOC-NEXT: S_BRANCH %bb.3
; REG_ALLOC-NEXT: {{ $}}
; REG_ALLOC-NEXT: bb.2:
; REG_ALLOC-NEXT: successors: %bb.1(0x80000000)
; REG_ALLOC-NEXT: liveins: $sgpr0, $sgpr1, $vgpr10, $sgpr4_sgpr5, $sgpr6_sgpr7
; REG_ALLOC-NEXT: {{ $}}
; REG_ALLOC-NEXT: renamable $sgpr1 = S_OR_B32 killed renamable $sgpr1, 2, implicit-def dead $scc
; REG_ALLOC-NEXT: renamable $vgpr8 = COPY killed renamable $sgpr1
; REG_ALLOC-NEXT: renamable $vgpr11_vgpr12 = IMPLICIT_DEF
; REG_ALLOC-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF
; REG_ALLOC-NEXT: S_BRANCH %bb.1
; REG_ALLOC-NEXT: {{ $}}
; REG_ALLOC-NEXT: bb.3:
; REG_ALLOC-NEXT: successors: %bb.5(0x80000000)
; REG_ALLOC-NEXT: liveins: $sgpr0, $vgpr10, $sgpr2_sgpr3, $sgpr4_sgpr5, $vgpr11_vgpr12_vgpr13_vgpr14:0x0000000000000003, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7:0x0000000000000300
; REG_ALLOC-NEXT: {{ $}}
; REG_ALLOC-NEXT: renamable $sgpr1 = V_READFIRSTLANE_B32 killed $vgpr11, implicit $exec
; REG_ALLOC-NEXT: renamable $sgpr6 = V_READFIRSTLANE_B32 killed $vgpr4, implicit $exec
; REG_ALLOC-NEXT: S_CMP_EQ_U32 killed renamable $sgpr6, killed renamable $sgpr1, implicit-def $scc
; REG_ALLOC-NEXT: renamable $sgpr1 = S_CSELECT_B32 1, 0, implicit $scc
; REG_ALLOC-NEXT: renamable $vgpr8 = COPY killed renamable $sgpr1
; REG_ALLOC-NEXT: S_BRANCH %bb.5
; REG_ALLOC-NEXT: {{ $}}
; REG_ALLOC-NEXT: bb.4:
; REG_ALLOC-NEXT: liveins: $sgpr0, $vgpr8, $vgpr10, $sgpr4_sgpr5
; REG_ALLOC-NEXT: {{ $}}
; REG_ALLOC-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (invariant load (<4 x s32>), addrspace 4)
; REG_ALLOC-NEXT: renamable $vgpr0 = V_ADD_U32_e64 killed $sgpr0, killed $vgpr10, 0, implicit $exec
; REG_ALLOC-NEXT: BUFFER_STORE_DWORD_OFFEN_exact killed renamable $vgpr8, killed renamable $vgpr0, killed renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s32), align 1, addrspace 8)
; REG_ALLOC-NEXT: S_ENDPGM 0
; REG_ALLOC-NEXT: {{ $}}
; REG_ALLOC-NEXT: bb.5:
; REG_ALLOC-NEXT: successors: %bb.4(0x80000000)
; REG_ALLOC-NEXT: liveins: $sgpr0, $vgpr8, $vgpr10, $sgpr2_sgpr3, $sgpr4_sgpr5
; REG_ALLOC-NEXT: {{ $}}
; REG_ALLOC-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr2_sgpr3, implicit-def $scc
; REG_ALLOC-NEXT: S_BRANCH %bb.4
;
; DEAD_INST_DEL-LABEL: name: _amdgpu_cs_main
; DEAD_INST_DEL: bb.0:
; DEAD_INST_DEL-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; DEAD_INST_DEL-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr10, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11
; DEAD_INST_DEL-NEXT: {{ $}}
; DEAD_INST_DEL-NEXT: renamable $vgpr5_vgpr6_vgpr7_vgpr8 = BUFFER_LOAD_DWORDX4_OFFEN renamable $vgpr3, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
; DEAD_INST_DEL-NEXT: renamable $vgpr15_vgpr16_vgpr17_vgpr18 = BUFFER_LOAD_DWORDX4_OFFEN renamable $vgpr2, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
; DEAD_INST_DEL-NEXT: renamable $vgpr11_vgpr12_vgpr13_vgpr14 = BUFFER_LOAD_DWORDX4_OFFEN renamable $vgpr0, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
; DEAD_INST_DEL-NEXT: KILL killed renamable $vgpr2
; DEAD_INST_DEL-NEXT: KILL killed renamable $vgpr0
; DEAD_INST_DEL-NEXT: KILL killed renamable $vgpr3
; DEAD_INST_DEL-NEXT: renamable $sgpr12 = V_READFIRSTLANE_B32 killed $vgpr5, implicit $exec
; DEAD_INST_DEL-NEXT: renamable $vgpr4_vgpr5_vgpr6_vgpr7 = BUFFER_LOAD_DWORDX4_OFFEN killed renamable $vgpr4, killed renamable $sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
; DEAD_INST_DEL-NEXT: renamable $sgpr13 = V_READFIRSTLANE_B32 killed $vgpr15, implicit $exec
; DEAD_INST_DEL-NEXT: renamable $sgpr6_sgpr7 = V_CMP_NE_U32_e64 killed $vgpr1, 0, implicit $exec
; DEAD_INST_DEL-NEXT: S_CMP_EQ_U64 killed renamable $sgpr12_sgpr13, killed renamable $sgpr2_sgpr3, implicit-def $scc
; DEAD_INST_DEL-NEXT: renamable $sgpr1 = S_CSELECT_B32 1, 0, implicit $scc
; DEAD_INST_DEL-NEXT: renamable $vgpr8 = IMPLICIT_DEF
; DEAD_INST_DEL-NEXT: $exec = S_MOV_B64_term renamable $sgpr6_sgpr7
; DEAD_INST_DEL-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
; DEAD_INST_DEL-NEXT: S_BRANCH %bb.2
; DEAD_INST_DEL-NEXT: {{ $}}
; DEAD_INST_DEL-NEXT: bb.1:
; DEAD_INST_DEL-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)
; DEAD_INST_DEL-NEXT: liveins: $sgpr0, $vgpr8, $vgpr10, $sgpr4_sgpr5, $sgpr6_sgpr7, $vgpr11_vgpr12_vgpr13_vgpr14:0x0000000000000003, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7:0x0000000000000300
; DEAD_INST_DEL-NEXT: {{ $}}
; DEAD_INST_DEL-NEXT: renamable $sgpr2_sgpr3 = S_OR_SAVEEXEC_B64 killed renamable $sgpr6_sgpr7, implicit-def $exec, implicit-def $scc, implicit $exec
; DEAD_INST_DEL-NEXT: $exec = S_XOR_B64_term $exec, renamable $sgpr2_sgpr3, implicit-def $scc
; DEAD_INST_DEL-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
; DEAD_INST_DEL-NEXT: S_BRANCH %bb.3
; DEAD_INST_DEL-NEXT: {{ $}}
; DEAD_INST_DEL-NEXT: bb.2:
; DEAD_INST_DEL-NEXT: successors: %bb.1(0x80000000)
; DEAD_INST_DEL-NEXT: liveins: $sgpr0, $sgpr1, $vgpr10, $sgpr4_sgpr5, $sgpr6_sgpr7
; DEAD_INST_DEL-NEXT: {{ $}}
; DEAD_INST_DEL-NEXT: renamable $sgpr1 = S_OR_B32 killed renamable $sgpr1, 2, implicit-def dead $scc
; DEAD_INST_DEL-NEXT: renamable $vgpr8 = COPY killed renamable $sgpr1
; DEAD_INST_DEL-NEXT: renamable $vgpr11_vgpr12 = IMPLICIT_DEF
; DEAD_INST_DEL-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF
; DEAD_INST_DEL-NEXT: S_BRANCH %bb.1
; DEAD_INST_DEL-NEXT: {{ $}}
; DEAD_INST_DEL-NEXT: bb.3:
; DEAD_INST_DEL-NEXT: successors: %bb.5(0x80000000)
; DEAD_INST_DEL-NEXT: liveins: $sgpr0, $vgpr10, $sgpr2_sgpr3, $sgpr4_sgpr5, $vgpr11_vgpr12_vgpr13_vgpr14:0x0000000000000003, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7:0x0000000000000300
; DEAD_INST_DEL-NEXT: {{ $}}
; DEAD_INST_DEL-NEXT: renamable $sgpr1 = V_READFIRSTLANE_B32 killed $vgpr11, implicit $exec
; DEAD_INST_DEL-NEXT: renamable $sgpr6 = V_READFIRSTLANE_B32 killed $vgpr4, implicit $exec
; DEAD_INST_DEL-NEXT: S_CMP_EQ_U32 killed renamable $sgpr6, killed renamable $sgpr1, implicit-def $scc
; DEAD_INST_DEL-NEXT: renamable $sgpr1 = S_CSELECT_B32 1, 0, implicit $scc
; DEAD_INST_DEL-NEXT: renamable $vgpr8 = COPY killed renamable $sgpr1
; DEAD_INST_DEL-NEXT: S_BRANCH %bb.5
; DEAD_INST_DEL-NEXT: {{ $}}
; DEAD_INST_DEL-NEXT: bb.4:
; DEAD_INST_DEL-NEXT: liveins: $sgpr0, $vgpr8, $vgpr10, $sgpr4_sgpr5
; DEAD_INST_DEL-NEXT: {{ $}}
; DEAD_INST_DEL-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (invariant load (<4 x s32>), addrspace 4)
; DEAD_INST_DEL-NEXT: renamable $vgpr0 = V_ADD_U32_e64 killed $sgpr0, killed $vgpr10, 0, implicit $exec
; DEAD_INST_DEL-NEXT: BUFFER_STORE_DWORD_OFFEN_exact killed renamable $vgpr8, killed renamable $vgpr0, killed renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s32), align 1, addrspace 8)
; DEAD_INST_DEL-NEXT: S_ENDPGM 0
; DEAD_INST_DEL-NEXT: {{ $}}
; DEAD_INST_DEL-NEXT: bb.5:
; DEAD_INST_DEL-NEXT: successors: %bb.4(0x80000000)
; DEAD_INST_DEL-NEXT: liveins: $sgpr0, $vgpr8, $vgpr10, $sgpr2_sgpr3, $sgpr4_sgpr5
; DEAD_INST_DEL-NEXT: {{ $}}
; DEAD_INST_DEL-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr2_sgpr3, implicit-def $scc
; DEAD_INST_DEL-NEXT: S_BRANCH %bb.4
bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $sgpr0, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr10
%0:sreg_32 = COPY $sgpr0
%1:vgpr_32 = COPY $vgpr0
%2:vgpr_32 = COPY $vgpr1
%3:vgpr_32 = COPY $vgpr2
%4:vgpr_32 = COPY $vgpr3
%5:vgpr_32 = COPY $vgpr4
%6:vgpr_32 = COPY $vgpr10
%7:sreg_64 = COPY $sgpr2_sgpr3
%8:sreg_64 = COPY $sgpr4_sgpr5
%9:sgpr_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
undef %10.sub0_sub1_sub2_sub3:vreg_256 = BUFFER_LOAD_DWORDX4_OFFEN %1, %9, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
%10.sub4_sub5_sub6_sub7:vreg_256 = BUFFER_LOAD_DWORDX4_OFFEN %5, %9, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
%11:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN %4, %9, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
%12:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN %3, %9, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
undef %13.sub0:sgpr_256 = V_READFIRSTLANE_B32 %11.sub0, implicit $exec
%13.sub1:sgpr_256 = V_READFIRSTLANE_B32 %12.sub0, implicit $exec
S_CMP_EQ_U64 %13.sub0_sub1, %7, implicit-def $scc
%14:sreg_32 = S_CSELECT_B32 1, 0, implicit killed $scc
%15:sreg_64_xexec = V_CMP_NE_U32_e64 %2, 0, implicit $exec
%16:vgpr_32 = IMPLICIT_DEF
$exec = S_MOV_B64_term %15
S_CBRANCH_EXECZ %bb.1, implicit $exec
S_BRANCH %bb.2
bb.1:
successors: %bb.3(0x40000000), %bb.5(0x40000000)
%17:sreg_64 = S_OR_SAVEEXEC_B64 %15, implicit-def $exec, implicit-def $scc, implicit $exec
%18:sreg_64_xexec = S_AND_B64 $exec, %17, implicit-def $scc
$exec = S_XOR_B64_term $exec, %18, implicit-def $scc
S_CBRANCH_EXECZ %bb.5, implicit $exec
S_BRANCH %bb.3
bb.2:
successors: %bb.1(0x80000000)
%19:sreg_32 = S_OR_B32 %14, 2, implicit-def dead $scc
%16:vgpr_32 = COPY %19
undef %10.sub0_sub1:vreg_256 = IMPLICIT_DEF
S_BRANCH %bb.1
bb.3:
successors: %bb.5(0x80000000)
%20:sreg_32_xm0 = V_READFIRSTLANE_B32 %10.sub0, implicit $exec
%21:sreg_32_xm0 = V_READFIRSTLANE_B32 %10.sub4, implicit $exec
S_CMP_EQ_U32 %21, %20, implicit-def $scc
%22:sreg_32 = S_CSELECT_B32 1, 0, implicit killed $scc
%16:vgpr_32 = COPY %22
S_BRANCH %bb.5
bb.4:
%23:vgpr_32 = V_ADD_U32_e64 %0, %6, 0, implicit $exec
%24:sgpr_128 = S_LOAD_DWORDX4_IMM %8, 0, 0 :: (invariant load (<4 x s32>), addrspace 4)
BUFFER_STORE_DWORD_OFFEN_exact %16, %23, %24, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s32), align 1, addrspace 8)
S_ENDPGM 0
bb.5:
successors: %bb.4(0x80000000)
$exec = S_OR_B64 $exec, %18, implicit-def $scc
S_BRANCH %bb.4
...
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