fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
53 lines
2.4 KiB
LLVM
53 lines
2.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11 %s
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s
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; GCN-LABEL: {{^}}lds_direct_load:
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; GCN: s_mov_b32 m0
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; GFX11: lds_direct_load v{{[0-9]+}}
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; GFX12: ds_direct_load v{{[0-9]+}}
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; GCN: s_mov_b32 m0
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; GFX11: lds_direct_load v{{[0-9]+}}
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; GFX12: ds_direct_load v{{[0-9]+}}
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; GCN: s_mov_b32 m0
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; GFX11: lds_direct_load v{{[0-9]+}}
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; GFX11: s_waitcnt expcnt(2)
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; GFX12: ds_direct_load v{{[0-9]+}}
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; GFX12: s_wait_expcnt 0x2
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; GCN: v_add_f32
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; GCN: buffer_store_b32
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; GFX11: s_waitcnt expcnt(1)
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; GFX12: s_wait_expcnt 0x1
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; GCN: buffer_store_b32
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; GFX11: s_waitcnt expcnt(0)
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; GFX12: s_wait_expcnt 0x0
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; GCN: buffer_store_b32
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; GCN: buffer_store_b32
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; GCN: buffer_store_b32
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; GCN: buffer_store_b32
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define amdgpu_ps void @lds_direct_load(ptr addrspace(8) inreg %buf, i32 inreg %arg0,
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i32 inreg %arg1, i32 inreg %arg2) #0 {
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main_body:
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%p0 = call float @llvm.amdgcn.lds.direct.load(i32 %arg0)
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; Ensure memory clustering is occuring for lds_direct_load
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%p5 = fadd float %p0, 1.0
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%p1 = call float @llvm.amdgcn.lds.direct.load(i32 %arg1)
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%p2 = call float @llvm.amdgcn.lds.direct.load(i32 %arg2)
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%p3 = call float @llvm.amdgcn.lds.direct.load(i32 %arg1)
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%p4 = call float @llvm.amdgcn.lds.direct.load(i32 %arg2)
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call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float %p5, ptr addrspace(8) %buf, i32 4, i32 0, i32 0)
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call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float %p1, ptr addrspace(8) %buf, i32 4, i32 1, i32 0)
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call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float %p2, ptr addrspace(8) %buf, i32 4, i32 2, i32 0)
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call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float %p3, ptr addrspace(8) %buf, i32 4, i32 3, i32 0)
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call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float %p4, ptr addrspace(8) %buf, i32 4, i32 4, i32 0)
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call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float %p0, ptr addrspace(8) %buf, i32 4, i32 5, i32 0)
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ret void
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}
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declare float @llvm.amdgcn.lds.direct.load(i32) #1
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declare void @llvm.amdgcn.raw.ptr.buffer.store.f32(float, ptr addrspace(8), i32, i32, i32)
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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