abc22f771e
Starting in gfx1250, voffset and immoffset are zero-extended from 32 bits to 45 bits before being added together.
196 lines
9.9 KiB
LLVM
196 lines
9.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx90a < %s | FileCheck -check-prefix=GFX90A %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx942 < %s | FileCheck -check-prefix=GFX942 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX1200 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250 %s
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define float @raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) #0 {
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; GFX90A-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX90A: ; %bb.0:
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; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX90A-NEXT: buffer_atomic_add_f32 v0, v1, s[16:19], s20 offen glc scc
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; GFX90A-NEXT: s_waitcnt vmcnt(0)
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; GFX90A-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX942-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX942: ; %bb.0:
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; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX942-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s16 offen sc0 sc1
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; GFX942-NEXT: s_waitcnt vmcnt(0)
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; GFX942-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1200-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX1200: ; %bb.0:
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; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1200-NEXT: s_wait_expcnt 0x0
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; GFX1200-NEXT: s_wait_samplecnt 0x0
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; GFX1200-NEXT: s_wait_bvhcnt 0x0
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; GFX1200-NEXT: s_wait_kmcnt 0x0
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; GFX1200-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s16 offen th:TH_ATOMIC_RETURN scope:SCOPE_SYS
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; GFX1200-NEXT: s_wait_loadcnt 0x0
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; GFX1200-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1250-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s16 offen th:TH_ATOMIC_RETURN scope:SCOPE_SYS
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; GFX1250-NEXT: s_wait_loadcnt 0x0
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; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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%ret = call float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 24)
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ret float %ret
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}
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define float @raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) #0 {
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; GFX90A-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX90A: ; %bb.0:
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; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX90A-NEXT: buffer_atomic_add_f32 v0, off, s[16:19], s20 glc
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; GFX90A-NEXT: s_waitcnt vmcnt(0)
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; GFX90A-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX942-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX942: ; %bb.0:
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; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX942-NEXT: buffer_atomic_add_f32 v0, off, s[0:3], s16 sc0
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; GFX942-NEXT: s_waitcnt vmcnt(0)
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; GFX942-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1200-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX1200: ; %bb.0:
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; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1200-NEXT: s_wait_expcnt 0x0
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; GFX1200-NEXT: s_wait_samplecnt 0x0
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; GFX1200-NEXT: s_wait_bvhcnt 0x0
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; GFX1200-NEXT: s_wait_kmcnt 0x0
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; GFX1200-NEXT: buffer_atomic_add_f32 v0, off, s[0:3], s16 th:TH_ATOMIC_RETURN
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; GFX1200-NEXT: s_wait_loadcnt 0x0
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; GFX1200-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1250-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: buffer_atomic_add_f32 v0, off, s[0:3], s16 th:TH_ATOMIC_RETURN
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; GFX1250-NEXT: s_wait_loadcnt 0x0
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; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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%ret = call float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 0, i32 %soffset, i32 0)
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ret float %ret
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}
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define <2 x half> @raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) #0 {
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; GFX90A-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX90A: ; %bb.0:
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; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX90A-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[16:19], s20 offen glc
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; GFX90A-NEXT: s_waitcnt vmcnt(0)
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; GFX90A-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX942-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX942: ; %bb.0:
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; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX942-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], s16 offen sc0
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; GFX942-NEXT: s_waitcnt vmcnt(0)
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; GFX942-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1200-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX1200: ; %bb.0:
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; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1200-NEXT: s_wait_expcnt 0x0
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; GFX1200-NEXT: s_wait_samplecnt 0x0
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; GFX1200-NEXT: s_wait_bvhcnt 0x0
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; GFX1200-NEXT: s_wait_kmcnt 0x0
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; GFX1200-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], s16 offen th:TH_ATOMIC_RETURN
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; GFX1200-NEXT: s_wait_loadcnt 0x0
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; GFX1200-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1250-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], s16 offen th:TH_ATOMIC_RETURN
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; GFX1250-NEXT: s_wait_loadcnt 0x0
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; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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%ret = call <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half> %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 0)
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ret <2 x half> %ret
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}
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define <2 x half> @raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(<2 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) #0 {
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; GFX90A-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX90A: ; %bb.0:
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; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX90A-NEXT: buffer_atomic_pk_add_f16 v0, off, s[16:19], s20 offset:92 glc
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; GFX90A-NEXT: s_waitcnt vmcnt(0)
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; GFX90A-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX942-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX942: ; %bb.0:
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; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX942-NEXT: buffer_atomic_pk_add_f16 v0, off, s[0:3], s16 offset:92 sc0
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; GFX942-NEXT: s_waitcnt vmcnt(0)
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; GFX942-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1200-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX1200: ; %bb.0:
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; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1200-NEXT: s_wait_expcnt 0x0
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; GFX1200-NEXT: s_wait_samplecnt 0x0
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; GFX1200-NEXT: s_wait_bvhcnt 0x0
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; GFX1200-NEXT: s_wait_kmcnt 0x0
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; GFX1200-NEXT: buffer_atomic_pk_add_f16 v0, off, s[0:3], s16 offset:92 th:TH_ATOMIC_RETURN
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; GFX1200-NEXT: s_wait_loadcnt 0x0
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; GFX1200-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1250-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: buffer_atomic_pk_add_f16 v0, off, s[0:3], s16 offset:92 th:TH_ATOMIC_RETURN
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; GFX1250-NEXT: s_wait_loadcnt 0x0
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; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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%ret = call <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half> %val, ptr addrspace(8) %rsrc, i32 92, i32 %soffset, i32 0)
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ret <2 x half> %ret
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}
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define float @raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) #0 {
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; GFX90A-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
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; GFX90A: ; %bb.0:
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; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX90A-NEXT: buffer_atomic_add_f32 v0, v1, s[16:19], s20 offen glc slc
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; GFX90A-NEXT: s_waitcnt vmcnt(0)
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; GFX90A-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX942-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
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; GFX942: ; %bb.0:
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; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX942-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s16 offen sc0 nt
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; GFX942-NEXT: s_waitcnt vmcnt(0)
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; GFX942-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1200-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
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; GFX1200: ; %bb.0:
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; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1200-NEXT: s_wait_expcnt 0x0
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; GFX1200-NEXT: s_wait_samplecnt 0x0
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; GFX1200-NEXT: s_wait_bvhcnt 0x0
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; GFX1200-NEXT: s_wait_kmcnt 0x0
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; GFX1200-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s16 offen th:TH_ATOMIC_NT_RETURN
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; GFX1200-NEXT: s_wait_loadcnt 0x0
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; GFX1200-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1250-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s16 offen th:TH_ATOMIC_NT_RETURN
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; GFX1250-NEXT: s_wait_loadcnt 0x0
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; GFX1250-NEXT: s_set_pc_i64 s[30:31]
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%ret = call float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 2)
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ret float %ret
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}
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declare float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float, ptr addrspace(8), i32, i32, i32 immarg)
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declare <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half>, ptr addrspace(8), i32, i32, i32 immarg)
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attributes #0 = { nounwind }
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