fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
110 lines
4.6 KiB
LLVM
110 lines
4.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,+real-true16 < %s | FileCheck -check-prefix=GFX11-TRUE16 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefix=GFX11-FAKE16 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global,+real-true16 < %s | FileCheck -check-prefix=GFX12-TRUE16 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefix=GFX12-FAKE16 %s
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declare half @llvm.amdgcn.rsq.f16(half %a)
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define amdgpu_kernel void @rsq_f16(
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; GCN-LABEL: rsq_f16:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: s_mov_b32 s10, s6
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; GCN-NEXT: s_mov_b32 s11, s7
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 s8, s2
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; GCN-NEXT: s_mov_b32 s9, s3
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; GCN-NEXT: buffer_load_ushort v0, off, s[8:11], 0
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; GCN-NEXT: s_mov_b32 s4, s0
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; GCN-NEXT: s_mov_b32 s5, s1
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_rsq_f16_e32 v0, v0
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; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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;
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; GFX11-TRUE16-LABEL: rsq_f16:
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; GFX11-TRUE16: ; %bb.0: ; %entry
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; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX11-TRUE16-NEXT: s_mov_b32 s6, -1
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; GFX11-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
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; GFX11-TRUE16-NEXT: s_mov_b32 s10, s6
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; GFX11-TRUE16-NEXT: s_mov_b32 s11, s7
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; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2
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; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3
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; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0
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; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0
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; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1
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; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
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; GFX11-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
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; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0
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; GFX11-TRUE16-NEXT: s_endpgm
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;
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; GFX11-FAKE16-LABEL: rsq_f16:
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; GFX11-FAKE16: ; %bb.0: ; %entry
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; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX11-FAKE16-NEXT: s_mov_b32 s6, -1
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; GFX11-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
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; GFX11-FAKE16-NEXT: s_mov_b32 s10, s6
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; GFX11-FAKE16-NEXT: s_mov_b32 s11, s7
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; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-FAKE16-NEXT: s_mov_b32 s8, s2
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; GFX11-FAKE16-NEXT: s_mov_b32 s9, s3
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; GFX11-FAKE16-NEXT: s_mov_b32 s4, s0
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; GFX11-FAKE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0
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; GFX11-FAKE16-NEXT: s_mov_b32 s5, s1
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; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
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; GFX11-FAKE16-NEXT: v_rsq_f16_e32 v0, v0
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; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0
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; GFX11-FAKE16-NEXT: s_endpgm
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;
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; GFX12-TRUE16-LABEL: rsq_f16:
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; GFX12-TRUE16: ; %bb.0: ; %entry
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; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX12-TRUE16-NEXT: s_mov_b32 s6, -1
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; GFX12-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
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; GFX12-TRUE16-NEXT: s_mov_b32 s10, s6
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; GFX12-TRUE16-NEXT: s_mov_b32 s11, s7
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; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2
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; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3
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; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0
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; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], null
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; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1
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; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
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; GFX12-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
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; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
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; GFX12-TRUE16-NEXT: s_endpgm
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;
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; GFX12-FAKE16-LABEL: rsq_f16:
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; GFX12-FAKE16: ; %bb.0: ; %entry
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; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX12-FAKE16-NEXT: s_mov_b32 s6, -1
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; GFX12-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
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; GFX12-FAKE16-NEXT: s_mov_b32 s10, s6
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; GFX12-FAKE16-NEXT: s_mov_b32 s11, s7
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; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-FAKE16-NEXT: s_mov_b32 s8, s2
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; GFX12-FAKE16-NEXT: s_mov_b32 s9, s3
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; GFX12-FAKE16-NEXT: s_mov_b32 s4, s0
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; GFX12-FAKE16-NEXT: buffer_load_u16 v0, off, s[8:11], null
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; GFX12-FAKE16-NEXT: s_mov_b32 s5, s1
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; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
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; GFX12-FAKE16-NEXT: v_rsq_f16_e32 v0, v0
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; GFX12-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
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; GFX12-FAKE16-NEXT: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %a) {
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entry:
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%a.val = load half, ptr addrspace(1) %a
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%r.val = call half @llvm.amdgcn.rsq.f16(half %a.val)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; VI: {{.*}}
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