a33a84ee63
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test gfx940 and gfx941 are no longer supported. This is one of a series of PRs to remove them from the code base. This PR uses gfx942 instead of gfx940 and gfx941 in the test RUN-lines (unless there is already a RUN-line for gfx942). The only notable difference in the test output is that gfx942 does not force the use of sc0 and sc1 on stores while gfx940 and gfx941 do (cf. https://reviews.llvm.org/D149986). For SWDEV-512631
272 lines
14 KiB
LLVM
272 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii < %s | FileCheck -check-prefix=GFX7 %s
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; Not supported in gfx8 or gfx9, except 90a/940
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; xUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX9,GFX90A %s
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; xUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX942 %s
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define double @struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(double %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
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; GFX6-LABEL: struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: buffer_atomic_fmax_x2 v[0:1], v[2:3], s[16:19], s20 idxen offen glc
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX7-LABEL: struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: buffer_atomic_fmax_x2 v[0:1], v[2:3], s[16:19], s20 idxen offen glc
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; GFX7-NEXT: s_waitcnt vmcnt(0)
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
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ret double %ret
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}
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define double @struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_fmax__sgpr_soffset(double %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
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; GFX6-LABEL: struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_fmax__sgpr_soffset:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: buffer_atomic_fmax_x2 v[0:1], v[2:3], s[16:19], s20 idxen offen offset:256 glc
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX7-LABEL: struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_fmax__sgpr_soffset:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: buffer_atomic_fmax_x2 v[0:1], v[2:3], s[16:19], s20 idxen offen offset:256 glc
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; GFX7-NEXT: s_waitcnt vmcnt(0)
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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%voffset.add = add i32 %voffset, 256
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%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset.add, i32 %soffset, i32 0)
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ret double %ret
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}
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define double @struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(double %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 inreg %soffset) {
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; GFX6-LABEL: struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: buffer_atomic_fmax_x2 v[0:1], v2, s[16:19], s20 idxen glc
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX7-LABEL: struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: buffer_atomic_fmax_x2 v[0:1], v2, s[16:19], s20 idxen glc
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; GFX7-NEXT: s_waitcnt vmcnt(0)
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 %soffset, i32 0)
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ret double %ret
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}
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define double @struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(double %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
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; GFX6-LABEL: struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: buffer_atomic_fmax_x2 v[0:1], v[2:3], s[16:19], s20 idxen offen glc slc
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX7-LABEL: struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: buffer_atomic_fmax_x2 v[0:1], v[2:3], s[16:19], s20 idxen offen glc slc
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; GFX7-NEXT: s_waitcnt vmcnt(0)
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 2)
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ret double %ret
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}
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define void @struct_ptr_buffer_atomic_fmax_f64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(double %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
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; GFX6-LABEL: struct_ptr_buffer_atomic_fmax_f64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: buffer_atomic_fmax_x2 v[0:1], v[2:3], s[16:19], s20 idxen offen
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX7-LABEL: struct_ptr_buffer_atomic_fmax_f64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: buffer_atomic_fmax_x2 v[0:1], v[2:3], s[16:19], s20 idxen offen
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; GFX7-NEXT: s_waitcnt vmcnt(0)
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
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ret void
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}
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define void @struct_ptr_buffer_atomic_fmax_f64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_fmax__sgpr_soffset(double %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
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; GFX6-LABEL: struct_ptr_buffer_atomic_fmax_f64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_fmax__sgpr_soffset:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: buffer_atomic_fmax_x2 v[0:1], v[2:3], s[16:19], s20 idxen offen offset:256
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX7-LABEL: struct_ptr_buffer_atomic_fmax_f64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_fmax__sgpr_soffset:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: buffer_atomic_fmax_x2 v[0:1], v[2:3], s[16:19], s20 idxen offen offset:256
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; GFX7-NEXT: s_waitcnt vmcnt(0)
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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%voffset.add = add i32 %voffset, 256
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%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset.add, i32 %soffset, i32 0)
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ret void
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}
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; Natural mapping, no voffset
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define void @struct_ptr_buffer_atomic_fmax_f64_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(double %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 inreg %soffset) {
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; GFX6-LABEL: struct_ptr_buffer_atomic_fmax_f64_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: buffer_atomic_fmax_x2 v[0:1], v2, s[16:19], s20 idxen
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX7-LABEL: struct_ptr_buffer_atomic_fmax_f64_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: buffer_atomic_fmax_x2 v[0:1], v2, s[16:19], s20 idxen
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; GFX7-NEXT: s_waitcnt vmcnt(0)
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 %soffset, i32 0)
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ret void
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}
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define void @struct_ptr_buffer_atomic_fmax_f64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(double %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
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; GFX6-LABEL: struct_ptr_buffer_atomic_fmax_f64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: buffer_atomic_fmax_x2 v[0:1], v[2:3], s[16:19], s20 idxen offen slc
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX7-LABEL: struct_ptr_buffer_atomic_fmax_f64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: buffer_atomic_fmax_x2 v[0:1], v[2:3], s[16:19], s20 idxen offen slc
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; GFX7-NEXT: s_waitcnt vmcnt(0)
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 2)
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ret void
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}
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; Test waterfall loop on resource
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define double @struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__vgpr_rsrc__vgpr_voffset_fmax__sgpr_soffset(double %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
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; GFX6-LABEL: struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__vgpr_rsrc__vgpr_voffset_fmax__sgpr_soffset:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: s_mov_b64 s[6:7], exec
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; GFX6-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
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; GFX6-NEXT: v_readfirstlane_b32 s8, v2
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; GFX6-NEXT: v_readfirstlane_b32 s9, v3
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; GFX6-NEXT: v_readfirstlane_b32 s10, v4
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; GFX6-NEXT: v_readfirstlane_b32 s11, v5
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; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[2:3]
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; GFX6-NEXT: v_cmp_eq_u64_e64 s[4:5], s[10:11], v[4:5]
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; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
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; GFX6-NEXT: s_and_saveexec_b64 s[4:5], s[4:5]
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; GFX6-NEXT: buffer_atomic_fmax_x2 v[0:1], v[6:7], s[8:11], s16 idxen offen offset:256 glc
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; GFX6-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
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; GFX6-NEXT: ; implicit-def: $vgpr6_vgpr7
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; GFX6-NEXT: s_xor_b64 exec, exec, s[4:5]
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; GFX6-NEXT: s_cbranch_execnz .LBB8_1
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; GFX6-NEXT: ; %bb.2:
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; GFX6-NEXT: s_mov_b64 exec, s[6:7]
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX7-LABEL: struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__vgpr_rsrc__vgpr_voffset_fmax__sgpr_soffset:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: s_mov_b64 s[6:7], exec
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; GFX7-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
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; GFX7-NEXT: v_readfirstlane_b32 s8, v2
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; GFX7-NEXT: v_readfirstlane_b32 s9, v3
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; GFX7-NEXT: v_readfirstlane_b32 s10, v4
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; GFX7-NEXT: v_readfirstlane_b32 s11, v5
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; GFX7-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[2:3]
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; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[10:11], v[4:5]
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; GFX7-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
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; GFX7-NEXT: s_and_saveexec_b64 s[4:5], s[4:5]
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; GFX7-NEXT: s_waitcnt vmcnt(0)
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; GFX7-NEXT: buffer_atomic_fmax_x2 v[0:1], v[6:7], s[8:11], s16 idxen offen offset:256 glc
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; GFX7-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
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; GFX7-NEXT: ; implicit-def: $vgpr6_vgpr7
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; GFX7-NEXT: s_xor_b64 exec, exec, s[4:5]
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; GFX7-NEXT: s_cbranch_execnz .LBB8_1
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; GFX7-NEXT: ; %bb.2:
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; GFX7-NEXT: s_mov_b64 exec, s[6:7]
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; GFX7-NEXT: s_waitcnt vmcnt(0)
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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%voffset.add = add i32 %voffset, 256
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%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset.add, i32 %soffset, i32 0)
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ret double %ret
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}
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; Test waterfall loop on soffset
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define double @struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_fmax__vgpr_soffset(double %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {
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; GFX6-LABEL: struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_fmax__vgpr_soffset:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: s_mov_b64 s[6:7], exec
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; GFX6-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
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; GFX6-NEXT: v_readfirstlane_b32 s8, v2
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; GFX6-NEXT: v_readfirstlane_b32 s9, v3
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; GFX6-NEXT: v_readfirstlane_b32 s10, v4
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; GFX6-NEXT: v_readfirstlane_b32 s11, v5
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; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[2:3]
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; GFX6-NEXT: v_cmp_eq_u64_e64 s[4:5], s[10:11], v[4:5]
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; GFX6-NEXT: v_readfirstlane_b32 s12, v8
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; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
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; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s12, v8
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; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], vcc
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; GFX6-NEXT: s_and_saveexec_b64 s[4:5], s[4:5]
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; GFX6-NEXT: buffer_atomic_fmax_x2 v[0:1], v[6:7], s[8:11], s12 idxen offen offset:256 glc
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; GFX6-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
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; GFX6-NEXT: ; implicit-def: $vgpr8
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; GFX6-NEXT: ; implicit-def: $vgpr6_vgpr7
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; GFX6-NEXT: s_xor_b64 exec, exec, s[4:5]
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; GFX6-NEXT: s_cbranch_execnz .LBB9_1
|
|
; GFX6-NEXT: ; %bb.2:
|
|
; GFX6-NEXT: s_mov_b64 exec, s[6:7]
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7-LABEL: struct_ptr_buffer_atomic_fmax_f64_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_fmax__vgpr_soffset:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7-NEXT: s_mov_b64 s[6:7], exec
|
|
; GFX7-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
|
|
; GFX7-NEXT: v_readfirstlane_b32 s8, v2
|
|
; GFX7-NEXT: v_readfirstlane_b32 s9, v3
|
|
; GFX7-NEXT: v_readfirstlane_b32 s10, v4
|
|
; GFX7-NEXT: v_readfirstlane_b32 s11, v5
|
|
; GFX7-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[2:3]
|
|
; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[10:11], v[4:5]
|
|
; GFX7-NEXT: v_readfirstlane_b32 s12, v8
|
|
; GFX7-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, s12, v8
|
|
; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GFX7-NEXT: s_and_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: buffer_atomic_fmax_x2 v[0:1], v[6:7], s[8:11], s12 idxen offen offset:256 glc
|
|
; GFX7-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
|
|
; GFX7-NEXT: ; implicit-def: $vgpr8
|
|
; GFX7-NEXT: ; implicit-def: $vgpr6_vgpr7
|
|
; GFX7-NEXT: s_xor_b64 exec, exec, s[4:5]
|
|
; GFX7-NEXT: s_cbranch_execnz .LBB9_1
|
|
; GFX7-NEXT: ; %bb.2:
|
|
; GFX7-NEXT: s_mov_b64 exec, s[6:7]
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: s_setpc_b64 s[30:31]
|
|
%voffset.add = add i32 %voffset, 256
|
|
%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset.add, i32 %soffset, i32 0)
|
|
ret double %ret
|
|
}
|
|
|
|
declare double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double, ptr addrspace(8), i32, i32, i32, i32 immarg)
|