fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
35 lines
1.4 KiB
LLVM
35 lines
1.4 KiB
LLVM
;RUN: llc < %s -mtriple=amdgcn -mcpu=verde -mattr=-promote-alloca | FileCheck %s -check-prefix=CHECK
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;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=-promote-alloca | FileCheck %s -check-prefix=CHECK
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; Allocate two stack slots of 2052 bytes each requiring a total of 4104 bytes.
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; Extracting the last element of each does not fit into the offset field of
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; MUBUF instructions, so a new base register is needed. This used to not
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; happen, leading to an assertion.
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; CHECK-LABEL: {{^}}main:
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; CHECK: buffer_store_dword
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; CHECK: buffer_store_dword
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; CHECK: buffer_load_dword
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; CHECK: buffer_load_dword
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define amdgpu_gs float @main(float %v1, float %v2, i32 %idx1, i32 %idx2) {
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main_body:
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%m1 = alloca [513 x float], addrspace(5)
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%m2 = alloca [513 x float], addrspace(5)
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%gep1.store = getelementptr [513 x float], ptr addrspace(5) %m1, i32 0, i32 %idx1
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store float %v1, ptr addrspace(5) %gep1.store
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%gep2.store = getelementptr [513 x float], ptr addrspace(5) %m2, i32 0, i32 %idx2
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store float %v2, ptr addrspace(5) %gep2.store
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; This used to use a base reg equal to 0.
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%out1 = load float, ptr addrspace(5) %m1
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; This used to attempt to re-use the base reg at 0, generating an out-of-bounds instruction offset.
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%gep2.load = getelementptr [513 x float], ptr addrspace(5) %m2, i32 0, i32 512
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%out2 = load float, ptr addrspace(5) %gep2.load
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%r = fadd float %out1, %out2
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ret float %r
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}
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