fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
30 lines
1.0 KiB
LLVM
30 lines
1.0 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GCN %s
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; In moveToVALU(), move to vector ALU is performed, all instrs in
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; the use chain will be visited. We do not want the same node to be
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; pushed to the visit worklist more than once.
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; GCN-LABEL: {{^}}in_worklist_once:
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; GCN: buffer_load_dword
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; GCN: BB0_1:
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; GCN: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @in_worklist_once() #0 {
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bb:
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%tmp = load i64, ptr addrspace(5) poison
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br label %bb1
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bb1: ; preds = %bb1, %bb
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%tmp2 = phi i64 [ poison, %bb ], [ %tmp16, %bb1 ]
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%tmp3 = phi i64 [ %tmp, %bb ], [ poison, %bb1 ]
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%tmp11 = shl i64 %tmp2, 14
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%tmp13 = xor i64 %tmp11, %tmp2
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%tmp15 = and i64 %tmp3, %tmp13
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%tmp16 = xor i64 %tmp15, %tmp3
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br label %bb1
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}
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attributes #0 = { nounwind }
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