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llvm-project/llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
Matt Arsenault ed38d6702f
PeepholeOpt: Handle subregister compose when looking through reg_sequence (#127051) 
Previously this would give up on folding subregister copies through
a reg_sequence if the input operand already had a subregister index.
d246cc618adc52fdbd69d44a2a375c8af97b6106 stopped introducing these
subregister uses, and this is the first step to lifting that restriction.

I was expecting to be able to implement this only purely with compose /
reverse compose, but I wasn't able to make it work so relies on testing
the lanemasks for whether the copy reads a subset of the input.
2025-02-18 08:07:29 +07:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -run-pass=peephole-opt -o - %s | FileCheck %s
# %2.sub0 -> %0.sub0
---
name: reg_sequence_extract_subreg_sub0_from_regsequence_sub0_sub1
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: reg_sequence_extract_subreg_sub0_from_regsequence_sub0_sub1
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]
%0:vreg_64_align2 = COPY $vgpr0_vgpr1
%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%2:vreg_64_align2 = REG_SEQUENCE %0.sub0, %subreg.sub0, %1, %subreg.sub1
%3:vgpr_32 = COPY %2.sub0
S_ENDPGM 0, implicit %3
...
# %2.sub1 -> %1
---
name: reg_sequence_extract_subreg_sub1_from_regsequence_sub0_sub1
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: reg_sequence_extract_subreg_sub1_from_regsequence_sub0_sub1
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B32_e32_]]
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]
%0:vreg_64_align2 = COPY $vgpr0_vgpr1
%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%2:vreg_64_align2 = REG_SEQUENCE %0.sub0, %subreg.sub0, %1, %subreg.sub1
%3:vgpr_32 = COPY %2.sub1
S_ENDPGM 0, implicit %3
...
# %2.sub0 -> %0.sub0
---
name: reg_sequence_extract_subreg_sub0_from_regsequence_sub1_sub0
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: reg_sequence_extract_subreg_sub0_from_regsequence_sub1_sub0
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub1, [[COPY]].sub0, %subreg.sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]
%0:vreg_64_align2 = COPY $vgpr0_vgpr1
%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%2:vreg_64_align2 = REG_SEQUENCE %1, %subreg.sub1, %0.sub0, %subreg.sub0
%3:vgpr_32 = COPY %2.sub0
S_ENDPGM 0, implicit %3
...
# %2.sub1 -> %1
---
name: reg_sequence_extract_subreg_sub1_from_regsequence_sub1_sub0
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: reg_sequence_extract_subreg_sub1_from_regsequence_sub1_sub0
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub1, [[COPY]].sub0, %subreg.sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B32_e32_]]
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]
%0:vreg_64_align2 = COPY $vgpr0_vgpr1
%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%2:vreg_64_align2 = REG_SEQUENCE %1, %subreg.sub1, %0.sub0, %subreg.sub0
%3:vgpr_32 = COPY %2.sub1
S_ENDPGM 0, implicit %3
...
# %2.sub0 -> %0.sub0
---
name: reg_sequence_extract_subreg_sub0_from_vreg96
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2
; CHECK-LABEL: name: reg_sequence_extract_subreg_sub0_from_vreg96
; CHECK: liveins: $vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[COPY]].sub1, %subreg.sub2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]
%0:vreg_64 = COPY $vgpr1_vgpr2
%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%2:vreg_96 = REG_SEQUENCE %0.sub0, %subreg.sub0, %1, %subreg.sub1, %0.sub1, %subreg.sub2
%3:vgpr_32 = COPY %2.sub0
S_ENDPGM 0, implicit %3
...
# %2.sub0 -> %0.sub0
---
name: reg_sequence_extract_subreg_sub1_from_vreg96
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2
; CHECK-LABEL: name: reg_sequence_extract_subreg_sub1_from_vreg96
; CHECK: liveins: $vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[COPY]].sub1, %subreg.sub2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]
%0:vreg_64 = COPY $vgpr1_vgpr2
%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%2:vreg_96 = REG_SEQUENCE %0.sub0, %subreg.sub0, %1, %subreg.sub1, %0.sub1, %subreg.sub2
%3:vgpr_32 = COPY %2.sub0
S_ENDPGM 0, implicit %3
...
---
name: reg_sequence_v128_compose_reg_sequence64_x2
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-LABEL: name: reg_sequence_v128_compose_reg_sequence64_x2
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY4]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
%2:vgpr_32 = COPY $vgpr2
%3:vgpr_32 = COPY $vgpr3
%4:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
%5:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
%6:vreg_128 = REG_SEQUENCE %4, %subreg.sub0_sub1, %5, %subreg.sub2_sub3
%7:vgpr_32 = COPY %6.sub2
S_ENDPGM 0, implicit %7
...
---
name: reg_sequence_v128_compose_reg_sequence128_subreg64_extract32_sub2
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-LABEL: name: reg_sequence_v128_compose_reg_sequence128_subreg64_extract32_sub2
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub0_sub1, %subreg.sub0, [[COPY1]], %subreg.sub2_sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]
%0:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7
%2:vreg_128 = REG_SEQUENCE %0.sub0_sub1, %subreg.sub0, %1, %subreg.sub2_sub3
%3:vgpr_32 = COPY %2.sub2
S_ENDPGM 0, implicit %3
...
---
name: reg_sequence_v128_align2_compose_reg_sequence128_subreg64_extract32_sub2
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-LABEL: name: reg_sequence_v128_align2_compose_reg_sequence128_subreg64_extract32_sub2
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]].sub0_sub1, %subreg.sub0, [[COPY1]], %subreg.sub2_sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]
%0:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7
%2:vreg_128_align2 = REG_SEQUENCE %0.sub0_sub1, %subreg.sub0, %1, %subreg.sub2_sub3
%3:vgpr_32 = COPY %2.sub2
S_ENDPGM 0, implicit %3
...
# Unhandled, spans multiple sources
---
name: reg_sequence_v128_align2_compose_reg_sequence128_subreg64_align2_extract64_sub1_sub2
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-LABEL: name: reg_sequence_v128_align2_compose_reg_sequence128_subreg64_align2_extract64_sub1_sub2
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]].sub0_sub1, %subreg.sub0, [[COPY1]], %subreg.sub2_sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]].sub1_sub2
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]
%0:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7
%2:vreg_128_align2 = REG_SEQUENCE %0.sub0_sub1, %subreg.sub0, %1, %subreg.sub2_sub3
%3:vreg_64_align2 = COPY %2.sub1_sub2
S_ENDPGM 0, implicit %3
...
# Unhandled, spans multiple sources
---
name: reg_sequence_v128_align2_compose_reg_sequence128_subreg64_align2_extract64_sub2_sub3
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-LABEL: name: reg_sequence_v128_align2_compose_reg_sequence128_subreg64_align2_extract64_sub2_sub3
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]].sub0_sub1, %subreg.sub0, [[COPY1]], %subreg.sub2_sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]].sub1_sub2
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]
%0:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7
%2:vreg_128_align2 = REG_SEQUENCE %0.sub0_sub1, %subreg.sub0, %1, %subreg.sub2_sub3
%3:vreg_64_align2 = COPY %2.sub1_sub2
S_ENDPGM 0, implicit %3
...
# %2.sub1 -> %0.sub1
---
name: reg_sequence_compose_0
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2
; CHECK-LABEL: name: reg_sequence_compose_0
; CHECK: liveins: $vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[V_MOV_B32_e32_]], %subreg.sub2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]
%0:vreg_64 = COPY $vgpr1_vgpr2
%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%2:vreg_96 = REG_SEQUENCE %0, %subreg.sub0_sub1, %1, %subreg.sub2
%3:vgpr_32 = COPY %2.sub1
S_ENDPGM 0, implicit %3
...
# %2.sub0 -> %0.sub2
# %2.sub1 -> %0.sub3
# %2.sub2 -> %0.sub0
---
name: reg_sequence_compose_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-LABEL: name: reg_sequence_compose_1
; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY]].sub0, %subreg.sub2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub2
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub3
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]]
%0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%2:vreg_96 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %0.sub0, %subreg.sub2
%3:vgpr_32 = COPY %2.sub0
%4:vgpr_32 = COPY %2.sub1
%5:vgpr_32 = COPY %2.sub2
S_ENDPGM 0, implicit %3, implicit %4, implicit %5
...
# %3.sub0 -> %0.sub2
---
name: reg_sequence_compose_2
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-LABEL: name: reg_sequence_compose_2
; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY]].sub0, %subreg.sub2, [[V_MOV_B32_e32_1]], %subreg.sub3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub2
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]
%0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
%3:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %0.sub0, %subreg.sub2, %2, %subreg.sub3
%4:vgpr_32 = COPY %3.sub0
S_ENDPGM 0, implicit %4
...
# %3.sub1 -> %0.sub3
# %3.sub0 -> %0.sub2
---
name: reg_sequence_compose_3
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-LABEL: name: reg_sequence_compose_3
; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY]].sub0, %subreg.sub2, [[V_MOV_B32_e32_1]], %subreg.sub3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub2
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
%0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
%3:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %0.sub0, %subreg.sub2, %2, %subreg.sub3
%4:vgpr_32 = COPY %3.sub1
%5:vgpr_32 = COPY %3.sub0
S_ENDPGM 0, implicit %4, implicit %5
...
# %3.sub2 -> %0.sub0
---
name: reg_sequence_compose_4
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-LABEL: name: reg_sequence_compose_4
; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY]].sub0, %subreg.sub2, [[V_MOV_B32_e32_1]], %subreg.sub3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]
%0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
%3:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %0.sub0, %subreg.sub2, %2, %subreg.sub3
%4:vgpr_32 = COPY %3.sub2
S_ENDPGM 0, implicit %4
...
# %2.sub3 -> %1.sub1
---
name: reg_sequence_compose_5
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: reg_sequence_compose_5
; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY1]].sub0_sub1, %subreg.sub2_sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]
%0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%1:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%2:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %1.sub0_sub1, %subreg.sub2_sub3
%3:vgpr_32 = COPY %2.sub3
S_ENDPGM 0, implicit %3
...
# %2.sub0 -> %0.sub2
---
name: reg_sequence_compose_6
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: reg_sequence_compose_6
; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY1]].sub0_sub1, %subreg.sub2_sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub2
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]
%0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%1:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%2:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %1.sub0_sub1, %subreg.sub2_sub3
%3:vgpr_32 = COPY %2.sub0
S_ENDPGM 0, implicit %3
...
# %2.sub1 -> %0.sub3
---
name: reg_sequence_compose_7
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: reg_sequence_compose_7
; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY1]].sub0_sub1, %subreg.sub2_sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub3
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]
%0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%1:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%2:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %1.sub0_sub1, %subreg.sub2_sub3
%3:vgpr_32 = COPY %2.sub1
S_ENDPGM 0, implicit %3
...
# %2.sub2 -> %1.sub0
---
name: reg_sequence_compose_8
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: reg_sequence_compose_8
; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY1]].sub0_sub1, %subreg.sub2_sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]
%0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%1:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%2:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %1.sub0_sub1, %subreg.sub2_sub3
%3:vgpr_32 = COPY %2.sub2
S_ENDPGM 0, implicit %3
...
# %2.sub3 -> %1.sub1
---
name: reg_sequence_compose_9
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: reg_sequence_compose_9
; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY1]].sub0_sub1, %subreg.sub2_sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]
%0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%1:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%2:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %1.sub0_sub1, %subreg.sub2_sub3
%3:vgpr_32 = COPY %2.sub3
S_ENDPGM 0, implicit %3
...
# %2.sub3 -> %1.sub1
---
name: reg_sequence_compose_10
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: reg_sequence_compose_10
; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]].sub0_sub1, %subreg.sub2_sub3, [[COPY]].sub2_sub3, %subreg.sub0_sub1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]
%0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%1:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%2:vreg_128 = REG_SEQUENCE %1.sub0_sub1, %subreg.sub2_sub3, %0.sub2_sub3, %subreg.sub0_sub1
%3:vgpr_32 = COPY %2.sub3
S_ENDPGM 0, implicit %3
...
# %2.sub1 -> %0.sub3
---
name: reg_sequence_compose_11
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: reg_sequence_compose_11
; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]].sub0_sub1, %subreg.sub2_sub3, [[COPY]].sub2_sub3, %subreg.sub0_sub1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub3
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]
%0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%1:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%2:vreg_128 = REG_SEQUENCE %1.sub0_sub1, %subreg.sub2_sub3, %0.sub2_sub3, %subreg.sub0_sub1
%3:vgpr_32 = COPY %2.sub1
S_ENDPGM 0, implicit %3
...
# %2.sub0 -> %0.sub1
---
name: reg_sequence_compose_12
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6
; CHECK-LABEL: name: reg_sequence_compose_12
; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr5_vgpr6
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub1_sub2_sub3, %subreg.sub0_sub1_sub2, [[COPY1]].sub1, %subreg.sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]
%0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%1:vreg_64 = COPY $vgpr5_vgpr6
%2:vreg_128 = REG_SEQUENCE %0.sub1_sub2_sub3, %subreg.sub0_sub1_sub2, %1.sub1, %subreg.sub3
%3:vgpr_32 = COPY %2.sub0
S_ENDPGM 0, implicit %3
...
# %2.sub0 -> %0.sub1
# %2.sub1 -> %0.sub2
# %2.sub2 -> %0.sub3
# %2.sub3 -> %1.sub1
---
name: reg_sequence_compose_13
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6
; CHECK-LABEL: name: reg_sequence_compose_13
; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr5_vgpr6
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub1_sub2_sub3, %subreg.sub0_sub1_sub2, [[COPY1]].sub1, %subreg.sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub2
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub3
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY4]], implicit [[COPY5]]
%0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%1:vreg_64 = COPY $vgpr5_vgpr6
%2:vreg_128 = REG_SEQUENCE %0.sub1_sub2_sub3, %subreg.sub0_sub1_sub2, %1.sub1, %subreg.sub3
%3:vgpr_32 = COPY %2.sub0
%4:vgpr_32 = COPY %2.sub1
%5:vgpr_32 = COPY %2.sub2
%6:vgpr_32 = COPY %2.sub3
S_ENDPGM 0, implicit %3, implicit %4, implicit %5, implicit %6
...
# %2.sub0 -> %0.sub1
# %2.sub1 -> %0.sub2
# %2.sub2 -> %1.sub0
# %2.sub3 -> %1.sub1
# %2.sub4 -> %0.sub2
# %2.sub5 -> %0.sub3
---
name: reg_sequence_compose_14
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6
; CHECK-LABEL: name: reg_sequence_compose_14
; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr5_vgpr6
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_192 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub4_sub5, [[COPY]].sub1_sub2, %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub2
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub2
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub3
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY6]], implicit [[COPY7]]
%0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%1:vreg_64 = COPY $vgpr5_vgpr6
%2:vreg_192 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub4_sub5, %0.sub1_sub2, %subreg.sub0_sub1, %1, %subreg.sub2_sub3
%3:vgpr_32 = COPY %2.sub0
%4:vgpr_32 = COPY %2.sub1
%5:vgpr_32 = COPY %2.sub2
%6:vgpr_32 = COPY %2.sub3
%7:vgpr_32 = COPY %2.sub4
%8:vgpr_32 = COPY %2.sub5
S_ENDPGM 0, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7, implicit %8
...
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