1377535d99
Before V_CNDMASK_B32_e64 gets converted to SDWA form, a conversion to V_CNDMASK_B32_e32 occurs. The vcc use of this instruction must be fixed into a vcc_lo use for wave32. This fix only happens after the final conversion to the SDWA form. This led to a compiler error in situations where the conversion to SDWA aborts. Make sure that the vcc-fix gets applied even if the SDWA conversion is not completed. --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
66 lines
3.3 KiB
LLVM
66 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck %s
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; In this test, V_CNDMASK_B32_e64 gets converted to V_CNDMASK_B32_e32,
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; but the expected conversion to SDWA does not occur. This led to a
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; compilation error, because the use of $vcc in the resulting
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; instruction must be fixed to $vcc_lo for wave32 which only happened
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; after the full conversion to SDWA.
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define void @quux(i32 %arg, i1 %arg1, i1 %arg2) {
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; CHECK-LABEL: quux:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v1, 1, v1
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 1, v1
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; CHECK-NEXT: v_mov_b32_e32 v1, 0
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; CHECK-NEXT: s_and_saveexec_b32 s4, vcc_lo
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; CHECK-NEXT: s_cbranch_execz .LBB0_2
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; CHECK-NEXT: ; %bb.1: ; %bb3
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; CHECK-NEXT: v_and_b32_e32 v1, 0x3ff, v31
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
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; CHECK-NEXT: v_mul_u32_u24_e32 v1, 5, v1
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; CHECK-NEXT: global_load_ushort v1, v[1:2], off offset:3
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; CHECK-NEXT: v_mov_b32_e32 v2, 0xffff
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_and_b32_sdwa v0, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
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; CHECK-NEXT: v_mov_b32_e32 v1, 24
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; CHECK-NEXT: v_mov_b32_e32 v2, 0xff
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; CHECK-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
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; CHECK-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
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; CHECK-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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; CHECK-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
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; CHECK-NEXT: .LBB0_2: ; %bb9
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; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: v_mov_b32_e32 v3, 0
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; CHECK-NEXT: global_store_byte v[2:3], v1, off
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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bb:
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br i1 %arg1, label %bb9, label %bb3
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bb3: ; preds = %bb
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%call = tail call i32 @llvm.amdgcn.workitem.id.x()
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%mul = mul i32 %call, 5
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%zext = zext i32 %mul to i64
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%getelementptr = getelementptr i8, ptr addrspace(1) null, i64 %zext
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%getelementptr4 = getelementptr i8, ptr addrspace(1) %getelementptr, i64 4
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%load = load i8, ptr addrspace(1) %getelementptr4, align 1
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%getelementptr5 = getelementptr i8, ptr addrspace(1) %getelementptr, i64 3
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%load6 = load i8, ptr addrspace(1) %getelementptr5, align 1
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%insertelement = insertelement <5 x i8> poison, i8 %load, i64 4
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%select = select i1 %arg2, <5 x i8> %insertelement, <5 x i8> <i8 poison, i8 poison, i8 poison, i8 poison, i8 0>
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%insertelement7 = insertelement <5 x i8> %select, i8 %load6, i64 0
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%icmp = icmp ult i32 0, %arg
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%select8 = select i1 %icmp, <5 x i8> zeroinitializer, <5 x i8> %insertelement7
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%shufflevector = shufflevector <5 x i8> zeroinitializer, <5 x i8> %select8, <5 x i32> <i32 0, i32 1, i32 7, i32 8, i32 9>
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br label %bb9
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bb9: ; preds = %bb3, %bb
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%phi = phi <5 x i8> [ %shufflevector, %bb3 ], [ zeroinitializer, %bb ]
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%extractelement = extractelement <5 x i8> %phi, i64 0
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store i8 %extractelement, ptr addrspace(1) null, align 1
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ret void
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}
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