9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
48 lines
2.0 KiB
LLVM
48 lines
2.0 KiB
LLVM
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
|
|
|
|
|
|
; Normally icmp + select is optimized to select_cc, when this happens the
|
|
; DAGLegalizer never sees the select and doesn't have a chance to leaglize it.
|
|
;
|
|
; In order to avoid the select_cc optimization, this test case calculates the
|
|
; condition for the select in a separate basic block.
|
|
|
|
; FUNC-LABEL: {{^}}select:
|
|
; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X
|
|
; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X
|
|
; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
|
|
; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
|
|
; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW
|
|
; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW
|
|
define amdgpu_kernel void @select (ptr addrspace(1) %i32out, ptr addrspace(1) %f32out,
|
|
ptr addrspace(1) %v2i32out, ptr addrspace(1) %v2f32out,
|
|
ptr addrspace(1) %v4i32out, ptr addrspace(1) %v4f32out,
|
|
i32 %cond) {
|
|
entry:
|
|
br label %for
|
|
body:
|
|
%inc = add i32 %i, 1
|
|
%br_cmp.i = icmp eq i1 %br_cmp, 0
|
|
br label %for
|
|
for:
|
|
%i = phi i32 [ %inc, %body], [ 0, %entry ]
|
|
%br_cmp = phi i1 [ %br_cmp.i, %body ], [ 0, %entry ]
|
|
%0 = icmp eq i32 %cond, %i
|
|
%1 = select i1 %br_cmp, i32 2, i32 3
|
|
%2 = select i1 %br_cmp, float 2.0 , float 5.0
|
|
%3 = select i1 %br_cmp, <2 x i32> <i32 2, i32 3>, <2 x i32> <i32 4, i32 5>
|
|
%4 = select i1 %br_cmp, <2 x float> <float 2.0, float 3.0>, <2 x float> <float 4.0, float 5.0>
|
|
%5 = select i1 %br_cmp, <4 x i32> <i32 2 , i32 3, i32 4, i32 5>, <4 x i32> <i32 6, i32 7, i32 8, i32 9>
|
|
%6 = select i1 %br_cmp, <4 x float> <float 2.0, float 3.0, float 4.0, float 5.0>, <4 x float> <float 6.0, float 7.0, float 8.0, float 9.0>
|
|
br i1 %0, label %body, label %done
|
|
|
|
done:
|
|
store i32 %1, ptr addrspace(1) %i32out
|
|
store float %2, ptr addrspace(1) %f32out
|
|
store <2 x i32> %3, ptr addrspace(1) %v2i32out
|
|
store <2 x float> %4, ptr addrspace(1) %v2f32out
|
|
store <4 x i32> %5, ptr addrspace(1) %v4i32out
|
|
store <4 x float> %6, ptr addrspace(1) %v4f32out
|
|
ret void
|
|
}
|