fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
70 lines
2.7 KiB
LLVM
70 lines
2.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}const_load_no_shrink_dword_to_unaligned_byte:
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; GCN: s_load_dword s{{[0-9]+}}
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; GCN: s_load_dword [[LD:s[0-9]+]],
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; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10013
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define amdgpu_kernel void @const_load_no_shrink_dword_to_unaligned_byte(ptr addrspace(1) %out, ptr addrspace(4) %in, i32 %x) {
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%ptr = getelementptr i32, ptr addrspace(4) %in, i32 %x
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%load = load i32, ptr addrspace(4) %ptr, align 4
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%and = and i32 %load, 524288
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%cmp = icmp eq i32 %and, 0
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%sel = select i1 %cmp, i32 0, i32 -1
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store i32 %sel, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: const_load_no_shrink_dword_to_aligned_byte:
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; GCN: s_load_dword s{{[0-9]+}}
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; GCN: s_load_dword [[LD:s[0-9]+]],
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; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10003
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define amdgpu_kernel void @const_load_no_shrink_dword_to_aligned_byte(ptr addrspace(1) %out, ptr addrspace(4) %in, i32 %x) {
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%ptr = getelementptr i32, ptr addrspace(4) %in, i32 %x
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%load = load i32, ptr addrspace(4) %ptr, align 4
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%and = and i32 %load, 8
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%cmp = icmp eq i32 %and, 0
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%sel = select i1 %cmp, i32 0, i32 -1
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store i32 %sel, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: global_load_no_shrink_dword_to_unaligned_byte:
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; GCN: s_load_dword s{{[0-9]+}}
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; GCN: s_load_dword [[LD:s[0-9]+]],
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; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10013
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define amdgpu_kernel void @global_load_no_shrink_dword_to_unaligned_byte(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i32 %x) {
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%ptr = getelementptr i32, ptr addrspace(1) %in, i32 %x
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%load = load i32, ptr addrspace(1) %ptr, align 4
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%and = and i32 %load, 524288
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%cmp = icmp eq i32 %and, 0
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%sel = select i1 %cmp, i32 0, i32 -1
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store i32 %sel, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: global_load_no_shrink_dword_to_aligned_byte:
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; GCN: s_load_dword s{{[0-9]+}}
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; GCN: s_load_dword [[LD:s[0-9]+]],
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; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10003
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define amdgpu_kernel void @global_load_no_shrink_dword_to_aligned_byte(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %x) {
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%ptr = getelementptr i32, ptr addrspace(1) %in, i32 %x
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%load = load i32, ptr addrspace(1) %ptr, align 4
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%and = and i32 %load, 8
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%cmp = icmp eq i32 %and, 0
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%sel = select i1 %cmp, i32 0, i32 -1
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store i32 %sel, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: const_load_shrink_dword_to_unaligned_byte:
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; GCN: global_load_ushort
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define amdgpu_kernel void @const_load_shrink_dword_to_unaligned_byte(ptr addrspace(1) %out, ptr addrspace(4) %in, i32 %x) {
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%ptr = getelementptr i32, ptr addrspace(4) %in, i32 %x
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%load = load i32, ptr addrspace(4) %ptr, align 2
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%and = and i32 %load, 524288
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%cmp = icmp eq i32 %and, 0
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%sel = select i1 %cmp, i32 0, i32 -1
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store i32 %sel, ptr addrspace(1) %out
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ret void
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}
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