9c58f3a234
MIParser checks that implicit operands match the instruction definition, so they have to be $vcc even in wave32 mode. Use the mirFileLoaded hook to fix them after MIParser's checks, converting them to $vcc_lo which is what that rest of CodeGen expects. This is all just extending the fixImplicitOperands hack which was introduced with GFX10, but at least it makes it possible to write a MIR test which creates the same instructions that normal CodeGen would generate.
152 lines
7.8 KiB
YAML
152 lines
7.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs -run-pass=si-i1-copies -o - %s | FileCheck -check-prefixes=GCN %s
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# Order in which SILowerI1Copies build instructions to merge lane masks should
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# not depend on order of incoming operands in phi instruction.
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# SDAG adds phi incomings as it processes basic blocks in reversed post order
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# traversal. Because of that, incomings in phis created by SDAG are sorted,
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# compared to the how phi looked in IR, in convenient way for lowerPhis.
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# Here incomings for %20:vreg_1 = PHI %19, %bb.1, %26, %bb.2 are swapped
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# to verify that SILowerI1Copies sorts incomings from phi appropriately before
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# it starts merging lane masks.
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---
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name: phi
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: phi
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x80000000)
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; GCN-NEXT: liveins: $vgpr1, $vgpr2, $vgpr3, $vgpr4
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr4
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
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; GCN-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1
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; GCN-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
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; GCN-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
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; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
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; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
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; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
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; GCN-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
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; GCN-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
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; GCN-NEXT: [[DEF4:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $exec_lo
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; GCN-NEXT: [[DEF5:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[PHI:%[0-9]+]]:sreg_32 = PHI [[DEF5]], %bb.0, %20, %bb.3
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; GCN-NEXT: [[PHI1:%[0-9]+]]:sreg_32 = PHI [[COPY6]], %bb.0, %37, %bb.3
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; GCN-NEXT: [[PHI2:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_1]], %bb.0, %16, %bb.3
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; GCN-NEXT: [[PHI3:%[0-9]+]]:vreg_64 = PHI [[COPY5]], %bb.0, %18, %bb.3
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; GCN-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[PHI1]]
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; GCN-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32 = S_ANDN2_B32 [[PHI]], $exec_lo, implicit-def $scc
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; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[PHI1]], $exec_lo, implicit-def $scc
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; GCN-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_ANDN2_B32_]], [[S_AND_B32_]], implicit-def $scc
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; GCN-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[COPY7]], %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.2
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: successors: %bb.3(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[PHI3]], 0, 0, implicit $exec :: (load (s32), addrspace 1)
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; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 killed [[GLOBAL_LOAD_DWORD]], killed [[S_MOV_B32_2]], implicit $exec
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; GCN-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32 = S_ANDN2_B32 [[S_OR_B32_]], $exec_lo, implicit-def $scc
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; GCN-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_EQ_U32_e64_]], $exec_lo, implicit-def $scc
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; GCN-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_ANDN2_B32_1]], [[S_AND_B32_1]], implicit-def $scc
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.3:
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; GCN-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[PHI4:%[0-9]+]]:sreg_32 = PHI [[S_OR_B32_]], %bb.1, [[S_OR_B32_1]], %bb.2
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; GCN-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 4
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; GCN-NEXT: [[V_ADD_U:%[0-9]+]]:vreg_64 = V_ADD_U64_PSEUDO [[PHI3]], killed [[S_MOV_B64_]], implicit-def dead $vcc_lo, implicit $exec
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; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 1
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; GCN-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = nsw S_ADD_I32 [[PHI2]], killed [[S_MOV_B32_3]], implicit-def dead $scc
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; GCN-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 9
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; GCN-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32 = S_ANDN2_B32 [[PHI1]], $exec_lo, implicit-def $scc
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; GCN-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32 = S_AND_B32 [[PHI4]], $exec_lo, implicit-def $scc
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; GCN-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_ANDN2_B32_2]], [[S_AND_B32_2]], implicit-def $scc
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; GCN-NEXT: S_CMP_GT_I32 [[S_ADD_I32_]], killed [[S_MOV_B32_4]], implicit-def $scc
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; GCN-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN-NEXT: S_BRANCH %bb.4
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.4:
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; GCN-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sgpr_32 = S_MOV_B32 1065353216
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; GCN-NEXT: [[S_MOV_B32_6:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
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; GCN-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[PHI1]]
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; GCN-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY killed [[S_MOV_B32_5]]
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; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, killed [[S_MOV_B32_6]], 0, [[COPY9]], [[COPY8]], implicit $exec
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; GCN-NEXT: FLAT_STORE_DWORD [[COPY4]], killed [[V_CNDMASK_B32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))
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; GCN-NEXT: SI_RETURN
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bb.0:
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successors: %bb.1(0x80000000)
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liveins: $vgpr1, $vgpr2, $vgpr3, $vgpr4
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%0:vgpr_32 = COPY $vgpr4
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%1:vgpr_32 = COPY $vgpr3
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%2:vgpr_32 = COPY $vgpr2
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%3:vgpr_32 = COPY $vgpr1
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%4:sgpr_32 = IMPLICIT_DEF
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%5:sgpr_32 = IMPLICIT_DEF
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%6:vreg_64 = REG_SEQUENCE %1, %subreg.sub0, %0, %subreg.sub1
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%7:sgpr_32 = IMPLICIT_DEF
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%8:sgpr_32 = IMPLICIT_DEF
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%9:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %2, %subreg.sub1
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%10:sreg_32 = S_MOV_B32 -1
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%11:sreg_32 = S_MOV_B32 -1
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%12:vreg_64 = COPY %6
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%13:vreg_64 = COPY %9
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%14:vreg_1 = COPY %10, implicit $exec
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bb.1:
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successors: %bb.2(0x40000000), %bb.3(0x40000000)
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%15:sreg_32 = PHI %11, %bb.0, %16, %bb.3
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%17:vreg_64 = PHI %13, %bb.0, %18, %bb.3
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%19:vreg_1 = PHI %14, %bb.0, %20, %bb.3
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%21:sreg_32 = COPY %19
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%22:sreg_32 = SI_IF %21, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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successors: %bb.3(0x80000000)
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%23:vgpr_32 = GLOBAL_LOAD_DWORD %17, 0, 0, implicit $exec :: (load (s32), addrspace 1)
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%24:sreg_32 = S_MOV_B32 0
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%25:sreg_32 = V_CMP_EQ_U32_e64 killed %23, killed %24, implicit $exec
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%26:vreg_1 = COPY %25
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bb.3:
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successors: %bb.4(0x04000000), %bb.1(0x7c000000)
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%20:vreg_1 = PHI %26, %bb.2, %19, %bb.1 ;%20:vreg_1 = PHI %19, %bb.1, %26, %bb.2 - this is original phi created by SDAG
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SI_END_CF %22, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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%27:sreg_64 = S_MOV_B64 4
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%18:vreg_64 = V_ADD_U64_PSEUDO %17, killed %27, implicit-def dead $vcc, implicit $exec
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%28:sreg_32 = S_MOV_B32 1
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%16:sreg_32 = nsw S_ADD_I32 %15, killed %28, implicit-def dead $scc
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%29:sreg_32 = S_MOV_B32 9
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S_CMP_GT_I32 %16, killed %29, implicit-def $scc
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S_CBRANCH_SCC1 %bb.1, implicit $scc
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S_BRANCH %bb.4
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bb.4:
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%30:vreg_1 = PHI %19, %bb.3
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%31:sgpr_32 = S_MOV_B32 1065353216
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%32:sgpr_32 = S_MOV_B32 0
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%33:sreg_32_xm0_xexec = COPY %30
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%34:vgpr_32 = COPY killed %31
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%35:vgpr_32 = V_CNDMASK_B32_e64 0, killed %32, 0, %34, %33, implicit $exec
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FLAT_STORE_DWORD %12, killed %35, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))
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SI_RETURN
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...
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