9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
91 lines
4.2 KiB
LLVM
91 lines
4.2 KiB
LLVM
; FIXME: The si scheduler crashes if when lane mask tracking is enabled, so
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; we need to disable this when the si scheduler is being used.
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; The only way the subtarget knows that the si machine scheduler is being used
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; is to specify -mattr=si-scheduler. If we just pass --misched=si, the backend
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; won't know what scheduler we are using.
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; RUN: llc -mtriple=amdgcn -mcpu=tahiti --misched=si -mattr=si-scheduler < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 --misched=si -mattr=si-scheduler < %s | FileCheck %s
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; The test checks the "si" machine scheduler pass works correctly.
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; CHECK-LABEL: {{^}}main:
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; CHECK: s_wqm
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; CHECK: s_load_dwordx8
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; CHECK: s_load_dwordx4
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; CHECK: s_waitcnt lgkmcnt(0)
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; CHECK: image_sample
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; CHECK: s_waitcnt vmcnt(0)
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; CHECK: exp
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; CHECK: s_endpgm
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define amdgpu_ps void @main(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, ptr addrspace(4) inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
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main_body:
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%tmp22 = load <32 x i8>, ptr addrspace(4) %arg3, align 32, !tbaa !0
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%tmp24 = load <16 x i8>, ptr addrspace(4) %arg2, align 16, !tbaa !0
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%i.i = extractelement <2 x i32> %arg11, i32 0
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%j.i = extractelement <2 x i32> %arg11, i32 1
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%i.f.i = bitcast i32 %i.i to float
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%j.f.i = bitcast i32 %j.i to float
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%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #1
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%p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #1
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%i.i1 = extractelement <2 x i32> %arg11, i32 0
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%j.i2 = extractelement <2 x i32> %arg11, i32 1
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%i.f.i3 = bitcast i32 %i.i1 to float
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%j.f.i4 = bitcast i32 %j.i2 to float
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%p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 1, i32 0, i32 %arg5) #1
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%p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 1, i32 0, i32 %arg5) #1
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%tmp22.bc = bitcast <32 x i8> %tmp22 to <8 x i32>
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%tmp24.bc = bitcast <16 x i8> %tmp24 to <4 x i32>
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%tmp31 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i, float %p2.i6, <8 x i32> %tmp22.bc, <4 x i32> %tmp24.bc, i1 0, i32 0, i32 0)
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%tmp32 = extractelement <4 x float> %tmp31, i32 0
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%tmp33 = extractelement <4 x float> %tmp31, i32 1
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%tmp34 = extractelement <4 x float> %tmp31, i32 2
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%tmp35 = extractelement <4 x float> %tmp31, i32 3
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%tmp36 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp32, float %tmp33)
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%tmp38 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp34, float %tmp35)
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp36, <2 x half> %tmp38, i1 true, i1 false) #0
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ret void
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}
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declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
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declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
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declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0
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declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
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declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind readonly }
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!0 = !{!1, !1, i64 0, i32 1}
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!1 = !{!"const", !2}
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!2 = !{!"tbaa root"}
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; CHECK-LABEL: amdgpu_ps_main:
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; CHECK: s_buffer_load_dword
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define amdgpu_ps void @_amdgpu_ps_main(i32 %arg) local_unnamed_addr {
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.entry:
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%tmp = insertelement <2 x i32> zeroinitializer, i32 %arg, i32 0
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%tmp1 = bitcast <2 x i32> %tmp to i64
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%tmp2 = inttoptr i64 %tmp1 to ptr addrspace(4)
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%tmp3 = load <4 x i32>, ptr addrspace(4) %tmp2, align 16
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%tmp4 = tail call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp3, i32 0, i32 0) #0
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switch i32 %tmp4, label %bb [
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i32 0, label %bb5
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i32 1, label %bb6
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]
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bb: ; preds = %.entry
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unreachable
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bb5: ; preds = %.entry
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unreachable
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bb6: ; preds = %.entry
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unreachable
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg) #1
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