fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
58 lines
1.6 KiB
LLVM
58 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; FIXME: merge with trap.ll
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; An s_cbranch_execnz is required to avoid trapping if all lanes are 0
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; GCN-LABEL: {{^}}trap_divergent_branch:
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; GCN: s_and_saveexec_b64
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; GCN: s_cbranch_execnz [[TRAP:.LBB[0-9]+_[0-9]+]]
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; GCN: ; %bb.{{[0-9]+}}:
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; GCN-NEXT: s_endpgm
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; GCN: [[TRAP]]:
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; GCN: s_trap 2
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @trap_divergent_branch(ptr addrspace(1) nocapture readonly %arg) {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %id
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%divergent.val = load i32, ptr addrspace(1) %gep
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%cmp = icmp eq i32 %divergent.val, 0
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br i1 %cmp, label %bb, label %end
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bb:
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call void @llvm.trap()
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br label %end
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end:
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ret void
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}
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; GCN-LABEL: {{^}}debugtrap_divergent_branch:
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; GCN: s_and_saveexec_b64
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; GCN: s_cbranch_execz [[ENDPGM:.LBB[0-9]+_[0-9]+]]
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; GCN: ; %bb.{{[0-9]+}}:
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; GCN: s_trap 3
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; GCN-NEXT: [[ENDPGM]]:
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @debugtrap_divergent_branch(ptr addrspace(1) nocapture readonly %arg) {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %id
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%divergent.val = load i32, ptr addrspace(1) %gep
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%cmp = icmp eq i32 %divergent.val, 0
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br i1 %cmp, label %bb, label %end
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bb:
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call void @llvm.debugtrap()
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br label %end
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end:
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ret void
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}
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declare void @llvm.trap() #0
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declare void @llvm.debugtrap() #1
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declare i32 @llvm.amdgcn.workitem.id.x() #2
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attributes #0 = { nounwind noreturn }
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attributes #1 = { nounwind }
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attributes #2 = { nounwind readnone speculatable }
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