ac0f64f06d
Allocating wwm-registers and per-thread VGPR operands together imposes many challenges in the way the registers are reused during allocation. There are times when regalloc reuses the registers of regular VGPRs operations for wwm-operations in a small range leading to unwantedly clobbering their inactive lanes causing correctness issues that are hard to trace. This patch splits the VGPR allocation pipeline further to allocate wwm-registers first and the regular VGPR operands in a separate pipeline. The splitting would ensure that the physical registers used for wwm allocations won't take part in the next allocation pipeline to avoid any such clobbering.
124 lines
5.8 KiB
YAML
124 lines
5.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=regallocfast -o - %s | FileCheck -check-prefix=SPILLED %s
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# RUN: llc -mtriple=amdgcn -mcpu=tahiti -passes=regallocfast -o - %s | FileCheck -check-prefix=SPILLED %s
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# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=regallocfast,si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=EXPANDED %s
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# RUN: llc -mtriple=amdgcn -mcpu=tahiti -passes=regallocfast,si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=EXPANDED %s
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# Make sure spill/restore of 192 bit registers works. We have to
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# settle for a MIR test for now since inlineasm fails without 192-bit
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# MVT.
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---
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name: spill_restore_sgpr192
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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stackPtrOffsetReg: $sgpr32
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body: |
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; SPILLED-LABEL: name: spill_restore_sgpr192
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; SPILLED: bb.0:
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; SPILLED-NEXT: successors: %bb.1(0x80000000)
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; SPILLED-NEXT: SI_SPILL_S192_SAVE killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s192) into %stack.0, align 4, addrspace 5)
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; SPILLED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: bb.1:
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; SPILLED-NEXT: successors: %bb.2(0x80000000)
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: S_NOP 1
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: bb.2:
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; SPILLED-NEXT: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 = SI_SPILL_S192_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s192) from %stack.0, align 4, addrspace 5)
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; SPILLED-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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;
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; EXPANDED-LABEL: name: spill_restore_sgpr192
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; EXPANDED: bb.0:
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; EXPANDED-NEXT: successors: %bb.1(0x80000000)
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, [[DEF]], implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr5, 1, [[DEF]]
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr6, 2, [[DEF]]
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr7, 3, [[DEF]]
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr8, 4, [[DEF]]
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr9, 5, [[DEF]], implicit killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: bb.1:
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; EXPANDED-NEXT: successors: %bb.2(0x80000000)
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: S_NOP 1
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: bb.2:
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; EXPANDED-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; EXPANDED-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 1
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; EXPANDED-NEXT: $sgpr6 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 2
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; EXPANDED-NEXT: $sgpr7 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 3
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; EXPANDED-NEXT: $sgpr8 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 4
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; EXPANDED-NEXT: $sgpr9 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 5
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; EXPANDED-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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bb.0:
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S_NOP 0, implicit-def %0:sgpr_192
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S_CBRANCH_SCC1 implicit undef $scc, %bb.1
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bb.1:
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S_NOP 1
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bb.2:
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S_NOP 0, implicit %0
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...
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---
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name: spill_restore_vgpr192
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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stackPtrOffsetReg: $sgpr32
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body: |
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; SPILLED-LABEL: name: spill_restore_vgpr192
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; SPILLED: bb.0:
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; SPILLED-NEXT: successors: %bb.1(0x80000000)
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
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; SPILLED-NEXT: SI_SPILL_V192_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, %stack.0, $sgpr32, 0, implicit $exec :: (store (s192) into %stack.0, align 4, addrspace 5)
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; SPILLED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: bb.1:
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; SPILLED-NEXT: successors: %bb.2(0x80000000)
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: S_NOP 1
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: bb.2:
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; SPILLED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V192_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s192) from %stack.0, align 4, addrspace 5)
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; SPILLED-NEXT: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
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;
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; EXPANDED-LABEL: name: spill_restore_vgpr192
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; EXPANDED: bb.0:
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; EXPANDED-NEXT: successors: %bb.1(0x80000000)
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
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; EXPANDED-NEXT: SI_SPILL_V192_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, %stack.0, $sgpr32, 0, implicit $exec :: (store (s192) into %stack.0, align 4, addrspace 5)
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; EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: bb.1:
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; EXPANDED-NEXT: successors: %bb.2(0x80000000)
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: S_NOP 1
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: bb.2:
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; EXPANDED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V192_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s192) from %stack.0, align 4, addrspace 5)
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; EXPANDED-NEXT: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
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bb.0:
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S_NOP 0, implicit-def %0:vreg_192
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S_CBRANCH_SCC1 implicit undef $scc, %bb.1
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bb.1:
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S_NOP 1
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bb.2:
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S_NOP 0, implicit %0
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...
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