fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
399 lines
15 KiB
LLVM
399 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,HAWAII %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,FIJI %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-TRUE16 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-FAKE16 %s
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define void @local_store_i56(ptr addrspace(3) %ptr, i56 %arg) #0 {
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; CIVI-LABEL: local_store_i56:
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; CIVI: ; %bb.0:
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; CIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CIVI-NEXT: s_mov_b32 m0, -1
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; CIVI-NEXT: ds_write_b16 v0, v2 offset:4
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; CIVI-NEXT: ds_write_b32 v0, v1
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; CIVI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
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; CIVI-NEXT: ds_write_b8 v0, v1 offset:6
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; CIVI-NEXT: s_waitcnt lgkmcnt(0)
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; CIVI-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: local_store_i56:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: ds_write_b8_d16_hi v0, v2 offset:6
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; GFX9-NEXT: ds_write_b16 v0, v2 offset:4
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; GFX9-NEXT: ds_write_b32 v0, v1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: local_store_i56:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: ds_write_b8_d16_hi v0, v2 offset:6
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; GFX10-NEXT: ds_write_b16 v0, v2 offset:4
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; GFX10-NEXT: ds_write_b32 v0, v1
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: local_store_i56:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: ds_store_b8_d16_hi v0, v2 offset:6
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; GFX11-NEXT: ds_store_b16 v0, v2 offset:4
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; GFX11-NEXT: ds_store_b32 v0, v1
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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store i56 %arg, ptr addrspace(3) %ptr, align 8
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ret void
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}
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define amdgpu_kernel void @local_store_i55(ptr addrspace(3) %ptr, i55 %arg) #0 {
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; HAWAII-LABEL: local_store_i55:
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; HAWAII: ; %bb.0:
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; HAWAII-NEXT: s_add_i32 s12, s12, s17
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; HAWAII-NEXT: s_or_b32 s0, s8, 14
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; HAWAII-NEXT: s_mov_b32 flat_scratch_lo, s13
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; HAWAII-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
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; HAWAII-NEXT: v_mov_b32_e32 v0, s0
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; HAWAII-NEXT: v_mov_b32_e32 v1, s9
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; HAWAII-NEXT: flat_load_ubyte v0, v[0:1]
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; HAWAII-NEXT: s_load_dword s2, s[8:9], 0x0
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; HAWAII-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x2
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; HAWAII-NEXT: s_mov_b32 m0, -1
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; HAWAII-NEXT: s_waitcnt lgkmcnt(0)
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; HAWAII-NEXT: v_mov_b32_e32 v1, s2
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; HAWAII-NEXT: v_mov_b32_e32 v2, s1
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; HAWAII-NEXT: v_mov_b32_e32 v3, s0
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; HAWAII-NEXT: ds_write_b16 v1, v2 offset:4
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; HAWAII-NEXT: s_waitcnt vmcnt(0)
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; HAWAII-NEXT: v_and_b32_e32 v0, 0x7f, v0
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; HAWAII-NEXT: ds_write_b8 v1, v0 offset:6
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; HAWAII-NEXT: ds_write_b32 v1, v3
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; HAWAII-NEXT: s_endpgm
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;
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; FIJI-LABEL: local_store_i55:
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; FIJI: ; %bb.0:
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; FIJI-NEXT: s_add_i32 s12, s12, s17
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; FIJI-NEXT: s_or_b32 s0, s8, 14
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; FIJI-NEXT: s_mov_b32 flat_scratch_lo, s13
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; FIJI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
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; FIJI-NEXT: v_mov_b32_e32 v0, s0
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; FIJI-NEXT: v_mov_b32_e32 v1, s9
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; FIJI-NEXT: flat_load_ubyte v0, v[0:1]
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; FIJI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
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; FIJI-NEXT: s_load_dword s2, s[8:9], 0x0
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; FIJI-NEXT: s_mov_b32 m0, -1
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; FIJI-NEXT: s_waitcnt lgkmcnt(0)
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; FIJI-NEXT: s_and_b32 s3, s1, 0xffff
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; FIJI-NEXT: v_mov_b32_e32 v1, s2
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; FIJI-NEXT: v_mov_b32_e32 v2, s1
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; FIJI-NEXT: v_mov_b32_e32 v3, s0
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; FIJI-NEXT: ds_write_b16 v1, v2 offset:4
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; FIJI-NEXT: s_waitcnt vmcnt(0)
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; FIJI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
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; FIJI-NEXT: v_or_b32_e32 v0, s3, v0
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; FIJI-NEXT: v_bfe_u32 v0, v0, 16, 7
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; FIJI-NEXT: ds_write_b8 v1, v0 offset:6
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; FIJI-NEXT: ds_write_b32 v1, v3
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; FIJI-NEXT: s_endpgm
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;
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; GFX9-LABEL: local_store_i55:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: global_load_ubyte_d16_hi v0, v0, s[8:9] offset:14
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
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; GFX9-NEXT: s_load_dword s2, s[8:9], 0x0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_and_b32 s3, s1, 0xffff
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; GFX9-NEXT: v_mov_b32_e32 v1, s2
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; GFX9-NEXT: v_mov_b32_e32 v2, s1
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; GFX9-NEXT: v_mov_b32_e32 v3, s0
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; GFX9-NEXT: ds_write_b16 v1, v2 offset:4
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_or_b32_e32 v0, s3, v0
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; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
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; GFX9-NEXT: ds_write_b8_d16_hi v1, v0 offset:6
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; GFX9-NEXT: ds_write_b32 v1, v3
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: local_store_i55:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-NEXT: s_clause 0x1
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; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
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; GFX10-NEXT: s_load_dword s2, s[8:9], 0x0
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; GFX10-NEXT: global_load_ubyte_d16_hi v0, v0, s[8:9] offset:14
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_and_b32 s3, s1, 0xffff
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; GFX10-NEXT: v_mov_b32_e32 v1, s2
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; GFX10-NEXT: v_mov_b32_e32 v2, s1
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; GFX10-NEXT: v_mov_b32_e32 v3, s0
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: v_or_b32_e32 v0, s3, v0
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; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
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; GFX10-NEXT: ds_write_b16 v1, v2 offset:4
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; GFX10-NEXT: ds_write_b8_d16_hi v1, v0 offset:6
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; GFX10-NEXT: ds_write_b32 v1, v3
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: local_store_i55:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
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; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x0
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; GFX11-NEXT: v_mov_b32_e32 v0, 0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_and_b32 s3, s1, 0xffff
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; GFX11-NEXT: v_mov_b32_e32 v1, s2
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; GFX11-NEXT: global_load_d16_hi_u8 v0, v0, s[4:5] offset:14
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; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v3, s0
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_or_b32_e32 v0, s3, v0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
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; GFX11-NEXT: ds_store_b8_d16_hi v1, v0 offset:6
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; GFX11-NEXT: ds_store_b16 v1, v2 offset:4
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; GFX11-NEXT: ds_store_b32 v1, v3
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; GFX11-NEXT: s_endpgm
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store i55 %arg, ptr addrspace(3) %ptr, align 8
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ret void
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}
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define amdgpu_kernel void @local_store_i48(ptr addrspace(3) %ptr, i48 %arg) #0 {
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; HAWAII-LABEL: local_store_i48:
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; HAWAII: ; %bb.0:
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; HAWAII-NEXT: s_load_dword s2, s[8:9], 0x0
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; HAWAII-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x2
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; HAWAII-NEXT: s_mov_b32 m0, -1
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; HAWAII-NEXT: s_waitcnt lgkmcnt(0)
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; HAWAII-NEXT: v_mov_b32_e32 v0, s2
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; HAWAII-NEXT: v_mov_b32_e32 v1, s1
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; HAWAII-NEXT: v_mov_b32_e32 v2, s0
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; HAWAII-NEXT: ds_write_b16 v0, v1 offset:4
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; HAWAII-NEXT: ds_write_b32 v0, v2
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; HAWAII-NEXT: s_endpgm
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;
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; FIJI-LABEL: local_store_i48:
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; FIJI: ; %bb.0:
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; FIJI-NEXT: s_load_dword s2, s[8:9], 0x0
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; FIJI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
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; FIJI-NEXT: s_mov_b32 m0, -1
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; FIJI-NEXT: s_waitcnt lgkmcnt(0)
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; FIJI-NEXT: v_mov_b32_e32 v0, s2
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; FIJI-NEXT: v_mov_b32_e32 v1, s1
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; FIJI-NEXT: v_mov_b32_e32 v2, s0
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; FIJI-NEXT: ds_write_b16 v0, v1 offset:4
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; FIJI-NEXT: ds_write_b32 v0, v2
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; FIJI-NEXT: s_endpgm
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;
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; GFX9-LABEL: local_store_i48:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dword s2, s[8:9], 0x0
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, s2
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; GFX9-NEXT: v_mov_b32_e32 v1, s1
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; GFX9-NEXT: v_mov_b32_e32 v2, s0
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; GFX9-NEXT: ds_write_b16 v0, v1 offset:4
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; GFX9-NEXT: ds_write_b32 v0, v2
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: local_store_i48:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_clause 0x1
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; GFX10-NEXT: s_load_dword s2, s[8:9], 0x0
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; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_mov_b32_e32 v0, s2
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; GFX10-NEXT: v_mov_b32_e32 v1, s1
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; GFX10-NEXT: v_mov_b32_e32 v2, s0
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; GFX10-NEXT: ds_write_b16 v0, v1 offset:4
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; GFX10-NEXT: ds_write_b32 v0, v2
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: local_store_i48:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x0
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; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s1
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; GFX11-NEXT: v_mov_b32_e32 v2, s0
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; GFX11-NEXT: ds_store_b16 v0, v1 offset:4
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; GFX11-NEXT: ds_store_b32 v0, v2
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; GFX11-NEXT: s_endpgm
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store i48 %arg, ptr addrspace(3) %ptr, align 8
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ret void
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}
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define amdgpu_kernel void @local_store_i65(ptr addrspace(3) %ptr, i65 %arg) #0 {
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; HAWAII-LABEL: local_store_i65:
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; HAWAII: ; %bb.0:
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; HAWAII-NEXT: s_load_dword s2, s[8:9], 0x4
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; HAWAII-NEXT: s_load_dword s3, s[8:9], 0x0
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; HAWAII-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x2
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; HAWAII-NEXT: s_mov_b32 m0, -1
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; HAWAII-NEXT: s_waitcnt lgkmcnt(0)
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; HAWAII-NEXT: s_and_b32 s2, s2, 1
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; HAWAII-NEXT: v_mov_b32_e32 v2, s3
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; HAWAII-NEXT: v_mov_b32_e32 v0, s2
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; HAWAII-NEXT: ds_write_b8 v2, v0 offset:8
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; HAWAII-NEXT: v_mov_b32_e32 v0, s0
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; HAWAII-NEXT: v_mov_b32_e32 v1, s1
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; HAWAII-NEXT: ds_write_b64 v2, v[0:1]
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; HAWAII-NEXT: s_endpgm
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;
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; FIJI-LABEL: local_store_i65:
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; FIJI: ; %bb.0:
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; FIJI-NEXT: s_load_dword s2, s[8:9], 0x10
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; FIJI-NEXT: s_load_dword s3, s[8:9], 0x0
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; FIJI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
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; FIJI-NEXT: s_mov_b32 m0, -1
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; FIJI-NEXT: s_waitcnt lgkmcnt(0)
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; FIJI-NEXT: s_and_b32 s2, s2, 1
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; FIJI-NEXT: v_mov_b32_e32 v2, s3
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; FIJI-NEXT: v_mov_b32_e32 v0, s2
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; FIJI-NEXT: ds_write_b8 v2, v0 offset:8
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; FIJI-NEXT: v_mov_b32_e32 v0, s0
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; FIJI-NEXT: v_mov_b32_e32 v1, s1
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; FIJI-NEXT: ds_write_b64 v2, v[0:1]
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; FIJI-NEXT: s_endpgm
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;
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; GFX9-LABEL: local_store_i65:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dword s2, s[8:9], 0x10
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; GFX9-NEXT: s_load_dword s3, s[8:9], 0x0
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_and_b32 s2, s2, 1
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; GFX9-NEXT: v_mov_b32_e32 v2, s3
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; GFX9-NEXT: v_mov_b32_e32 v0, s0
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; GFX9-NEXT: v_mov_b32_e32 v3, s2
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; GFX9-NEXT: v_mov_b32_e32 v1, s1
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; GFX9-NEXT: ds_write_b8 v2, v3 offset:8
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; GFX9-NEXT: ds_write_b64 v2, v[0:1]
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: local_store_i65:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_clause 0x2
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; GFX10-NEXT: s_load_dword s2, s[8:9], 0x10
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; GFX10-NEXT: s_load_dword s3, s[8:9], 0x0
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; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_and_b32 s2, s2, 1
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; GFX10-NEXT: v_mov_b32_e32 v2, s3
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; GFX10-NEXT: v_mov_b32_e32 v3, s2
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; GFX10-NEXT: v_mov_b32_e32 v0, s0
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; GFX10-NEXT: v_mov_b32_e32 v1, s1
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; GFX10-NEXT: ds_write_b8 v2, v3 offset:8
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; GFX10-NEXT: ds_write_b64 v2, v[0:1]
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: local_store_i65:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_clause 0x2
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; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x10
|
|
; GFX11-NEXT: s_load_b32 s3, s[4:5], 0x0
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: s_and_b32 s2, s2, 1
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mov_b32 v3, s2
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX11-NEXT: ds_store_b8 v2, v3 offset:8
|
|
; GFX11-NEXT: ds_store_b64 v2, v[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
store i65 %arg, ptr addrspace(3) %ptr, align 8
|
|
ret void
|
|
}
|
|
|
|
define void @local_store_i13(ptr addrspace(3) %ptr, i13 %arg) #0 {
|
|
; CIVI-LABEL: local_store_i13:
|
|
; CIVI: ; %bb.0:
|
|
; CIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; CIVI-NEXT: v_and_b32_e32 v1, 0x1fff, v1
|
|
; CIVI-NEXT: s_mov_b32 m0, -1
|
|
; CIVI-NEXT: ds_write_b16 v0, v1
|
|
; CIVI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; CIVI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: local_store_i13:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_and_b32_e32 v1, 0x1fff, v1
|
|
; GFX9-NEXT: ds_write_b16 v0, v1
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10-LABEL: local_store_i13:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10-NEXT: v_and_b32_e32 v1, 0x1fff, v1
|
|
; GFX10-NEXT: ds_write_b16 v0, v1
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: local_store_i13:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x1fff, v1.l
|
|
; GFX11-TRUE16-NEXT: ds_store_b16 v0, v1
|
|
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: local_store_i13:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0x1fff, v1
|
|
; GFX11-FAKE16-NEXT: ds_store_b16 v0, v1
|
|
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
store i13 %arg, ptr addrspace(3) %ptr, align 8
|
|
ret void
|
|
}
|
|
|
|
define void @local_store_i17(ptr addrspace(3) %ptr, i17 %arg) #0 {
|
|
; CIVI-LABEL: local_store_i17:
|
|
; CIVI: ; %bb.0:
|
|
; CIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; CIVI-NEXT: s_mov_b32 m0, -1
|
|
; CIVI-NEXT: ds_write_b16 v0, v1
|
|
; CIVI-NEXT: v_bfe_u32 v1, v1, 16, 1
|
|
; CIVI-NEXT: ds_write_b8 v0, v1 offset:2
|
|
; CIVI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; CIVI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: local_store_i17:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: ds_write_b16 v0, v1
|
|
; GFX9-NEXT: v_and_b32_e32 v1, 0x1ffff, v1
|
|
; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:2
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10-LABEL: local_store_i17:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10-NEXT: v_and_b32_e32 v2, 0x1ffff, v1
|
|
; GFX10-NEXT: ds_write_b16 v0, v1
|
|
; GFX10-NEXT: ds_write_b8_d16_hi v0, v2 offset:2
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: local_store_i17:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: v_and_b32_e32 v2, 0x1ffff, v1
|
|
; GFX11-NEXT: ds_store_b16 v0, v1
|
|
; GFX11-NEXT: ds_store_b8_d16_hi v0, v2 offset:2
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
store i17 %arg, ptr addrspace(3) %ptr, align 8
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { nounwind }
|