420a5de1a4
When using the `amdgcn.init.whole.wave` intrinsic, we add dummy VGPR arguments with the purpose of preserving their inactive lanes. The pattern may look something like this: ``` entry: call amdgcn.init.whole.wave branch to shader or tail shader: $vInactive = IMPLICIT_DEF ; Tells regalloc it's safe to use the active lanes actual code... tail: call amdgcn.cs.chain [...], implicit $vInactive ``` We should not report these VGPRs in the `.vgpr_count` metadata. This patch achieves that goal by ignoring meta instructions and calls. This should be safe since if those registers are actually used in any other context, they will be counted there. The same reasoning applies in the general case, so we don't explicitly check for the existence of `init.whole.wave`. This is a reworked version of #133242, which was reverted in #144039 and split into smaller bits.
27 lines
967 B
LLVM
27 lines
967 B
LLVM
; RUN: llc -mcpu=gfx1200 < %s | FileCheck %s
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target triple = "amdgcn--amdpal"
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@global = addrspace(1) global i32 poison, align 4
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; CHECK-LABEL: amdpal.pipelines:
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; Shouldn't report the part of %vgpr_args that's not used
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; CHECK-LABEL: entry_point_symbol: cs_calling_chain
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; CHECK: .vgpr_count: 0xa
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define amdgpu_cs void @cs_calling_chain(i32 %vgpr, i32 inreg %sgpr) {
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%vgpr_args = insertvalue {i32, i32, i32, i32} poison, i32 %vgpr, 1
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call void (ptr, i32, i32, {i32, i32, i32, i32}, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.i32.s(
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ptr @chain_func, i32 0, i32 inreg %sgpr, {i32, i32, i32, i32} %vgpr_args, i32 0)
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unreachable
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}
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; Neither uses not writes a VGPR
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; CHECK-LABEL: chain_func:
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; CHECK: .vgpr_count: 0x1
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define amdgpu_cs_chain void @chain_func([32 x i32] %args) {
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entry:
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call void (ptr, i32, {}, [32 x i32], i32, ...) @llvm.amdgcn.cs.chain.p0.i32.s.a(
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ptr @chain_func, i32 0, {} inreg {}, [32 x i32] %args, i32 0)
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unreachable
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}
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