fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
114 lines
4.4 KiB
LLVM
114 lines
4.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel=1 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
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define amdgpu_kernel void @workgroup_id_x(ptr addrspace(1) %ptrx) {
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;
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; GFX9-LABEL: workgroup_id_x:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; GFX9-NEXT: v_mov_b32_e32 v0, ttmp9
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX9-NEXT: s_endpgm
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;
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; GFX12-LABEL: workgroup_id_x:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
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; GFX12-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX12-NEXT: s_endpgm
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%idx = call i32 @llvm.amdgcn.workgroup.id.x()
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store i32 %idx, ptr addrspace(1) %ptrx
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ret void
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}
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define amdgpu_kernel void @workgroup_id_xy(ptr addrspace(1) %ptrx, ptr addrspace(1) %ptry) {
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; GFX9-LABEL: workgroup_id_xy:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; GFX9-NEXT: v_mov_b32_e32 v0, ttmp9
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: s_and_b32 s4, ttmp7, 0xffff
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; GFX9-NEXT: v_mov_b32_e32 v2, s4
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX9-NEXT: global_store_dword v1, v2, s[2:3]
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; GFX9-NEXT: s_endpgm
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;
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; GFX12-LABEL: workgroup_id_xy:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
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; GFX12-NEXT: s_and_b32 s4, ttmp7, 0xffff
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; GFX12-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0
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; GFX12-NEXT: v_mov_b32_e32 v2, s4
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_clause 0x1
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; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX12-NEXT: global_store_b32 v1, v2, s[2:3]
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; GFX12-NEXT: s_endpgm
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%idx = call i32 @llvm.amdgcn.workgroup.id.x()
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store i32 %idx, ptr addrspace(1) %ptrx
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%idy = call i32 @llvm.amdgcn.workgroup.id.y()
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store i32 %idy, ptr addrspace(1) %ptry
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ret void
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}
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define amdgpu_kernel void @workgroup_id_xyz(ptr addrspace(1) %ptrx, ptr addrspace(1) %ptry, ptr addrspace(1) %ptrz) {
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; GFX9-LABEL: workgroup_id_xyz:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
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; GFX9-NEXT: v_mov_b32_e32 v0, ttmp9
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: s_and_b32 s6, ttmp7, 0xffff
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX9-NEXT: v_mov_b32_e32 v0, s6
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; GFX9-NEXT: s_lshr_b32 s0, ttmp7, 16
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; GFX9-NEXT: global_store_dword v1, v0, s[2:3]
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; GFX9-NEXT: v_mov_b32_e32 v0, s0
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; GFX9-NEXT: global_store_dword v1, v0, s[4:5]
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; GFX9-NEXT: s_endpgm
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;
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; GFX12-LABEL: workgroup_id_xyz:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_clause 0x1
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; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
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; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x10
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; GFX12-NEXT: s_and_b32 s6, ttmp7, 0xffff
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; GFX12-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0
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; GFX12-NEXT: s_lshr_b32 s7, ttmp7, 16
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_clause 0x2
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; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX12-NEXT: global_store_b32 v1, v2, s[2:3]
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; GFX12-NEXT: global_store_b32 v1, v3, s[4:5]
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; GFX12-NEXT: s_endpgm
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%idx = call i32 @llvm.amdgcn.workgroup.id.x()
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store i32 %idx, ptr addrspace(1) %ptrx
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%idy = call i32 @llvm.amdgcn.workgroup.id.y()
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store i32 %idy, ptr addrspace(1) %ptry
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%idz = call i32 @llvm.amdgcn.workgroup.id.z()
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store i32 %idz, ptr addrspace(1) %ptrz
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ret void
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}
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declare i32 @llvm.amdgcn.workgroup.id.x()
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declare i32 @llvm.amdgcn.workgroup.id.y()
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declare i32 @llvm.amdgcn.workgroup.id.z()
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; GFX12-GISEL: {{.*}}
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; GFX12-SDAG: {{.*}}
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; GFX9-GISEL: {{.*}}
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; GFX9-SDAG: {{.*}}
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