dfb5b6e27c
Instead of failing to select during isel, drop the intrinsic in lowering. Similar as the X86's PR. Seeing: https://reviews.llvm.org/D151050. Fixes #134624
34 lines
1000 B
LLVM
34 lines
1000 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
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; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
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declare void @llvm.prefetch(ptr, i32, i32, i32) nounwind
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define dso_local void @prefetch_no_offset(ptr %ptr) nounwind {
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; LA32-LABEL: prefetch_no_offset:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ret
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;
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; LA64-LABEL: prefetch_no_offset:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ret
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entry:
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tail call void @llvm.prefetch(ptr %ptr, i32 0, i32 3, i32 0)
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ret void
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}
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define dso_local void @prefetch_with_offset(ptr %ptr) nounwind {
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; LA32-LABEL: prefetch_with_offset:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ret
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;
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; LA64-LABEL: prefetch_with_offset:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ret
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entry:
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%addr = getelementptr i8, ptr %ptr, i64 200
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tail call void @llvm.prefetch(ptr %addr, i32 0, i32 3, i32 0)
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ret void
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}
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