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llvm-project
/
llvm
/
test
/
Transforms
/
AggressiveInstCombine
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chenglin.bi
76df706bca
Revert "[LogicCombine 1/?] Implement a general way to simplify logical operations."
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This reverts commit 97dcbea63e11d566cff0cd3a758cf1114cf1f633.
2023-03-14 09:00:06 +08:00
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AArch64
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ARM
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X86
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funnel.ll
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logic-combine.ll
Revert "[LogicCombine 1/?] Implement a general way to simplify logical operations."
2023-03-14 09:00:06 +08:00
lower-table-based-cttz-basics.ll
[InstCombine] Improvement the analytics through the dominating condition
2023-03-01 17:03:34 +08:00
lower-table-based-cttz-dereferencing-pointer.ll
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lower-table-based-cttz-non-argument-value.ll
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lower-table-based-cttz-zero-element.ll
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masked-cmp.ll
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negative-lower-table-based-cttz.ll
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popcount.ll
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pr50555.ll
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rotate.ll
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trunc_ashr.ll
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trunc_assume.ll
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trunc_const_expr.ll
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trunc_lshr.ll
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trunc_multi_uses.ll
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trunc_phi.ll
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trunc_select_cmp.ll
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trunc_select.ll
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trunc_shl.ll
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trunc_udivrem.ll
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trunc_unreachable_bb.ll
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trunc_vector_instrs.ll
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vector-or-load.ll
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