9db13b5a7d
This adds support for constrained floating-point comparison intrinsics.
Specifically, we add:
declare <ty2>
@llvm.experimental.constrained.fcmp(<type> <op1>, <type> <op2>,
metadata <condition code>,
metadata <exception behavior>)
declare <ty2>
@llvm.experimental.constrained.fcmps(<type> <op1>, <type> <op2>,
metadata <condition code>,
metadata <exception behavior>)
The first variant implements an IEEE "quiet" comparison (i.e. we only
get an invalid FP exception if either argument is a SNaN), while the
second variant implements an IEEE "signaling" comparison (i.e. we get
an invalid FP exception if either argument is any NaN).
The condition code is implemented as a metadata string. The same set
of predicates as for the fcmp instruction is supported (except for the
"true" and "false" predicates).
These new intrinsics are mapped by SelectionDAG codegen onto two new
ISD opcodes, ISD::STRICT_FSETCC and ISD::STRICT_FSETCCS, again
representing quiet vs. signaling comparison operations. Otherwise
those nodes look like SETCC nodes, with an additional chain argument
and result as usual for strict FP nodes. The patch includes support
for the common legalization operations for those nodes.
The patch also includes full SystemZ back-end support for the new
ISD nodes, mapping them to all available SystemZ instruction to
fully implement strict semantics (scalar and vector).
Differential Revision: https://reviews.llvm.org/D69281
388 lines
12 KiB
C++
388 lines
12 KiB
C++
//===-- SystemZShortenInst.cpp - Instruction-shortening pass --------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass tries to replace instructions with shorter forms. For example,
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// IILF can be replaced with LLILL or LLILH if the constant fits and if the
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// other 32 bits of the GR64 destination are not live.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZTargetMachine.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "systemz-shorten-inst"
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namespace {
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class SystemZShortenInst : public MachineFunctionPass {
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public:
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static char ID;
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SystemZShortenInst(const SystemZTargetMachine &tm);
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StringRef getPassName() const override {
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return "SystemZ Instruction Shortening";
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}
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bool processBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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private:
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bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
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bool shortenOn0(MachineInstr &MI, unsigned Opcode);
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bool shortenOn01(MachineInstr &MI, unsigned Opcode);
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bool shortenOn001(MachineInstr &MI, unsigned Opcode);
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bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
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bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
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bool shortenSelect(MachineInstr &MI, unsigned Opcode);
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const SystemZInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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LivePhysRegs LiveRegs;
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};
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char SystemZShortenInst::ID = 0;
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} // end anonymous namespace
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FunctionPass *llvm::createSystemZShortenInstPass(SystemZTargetMachine &TM) {
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return new SystemZShortenInst(TM);
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}
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SystemZShortenInst::SystemZShortenInst(const SystemZTargetMachine &tm)
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: MachineFunctionPass(ID), TII(nullptr) {}
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// Tie operands if MI has become a two-address instruction.
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static void tieOpsIfNeeded(MachineInstr &MI) {
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if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
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!MI.getOperand(0).isTied())
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MI.tieOperands(0, 1);
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}
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// MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
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// are the halfword immediate loads for the same word. Try to use one of them
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// instead of IIxF.
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bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned LLIxL,
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unsigned LLIxH) {
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Register Reg = MI.getOperand(0).getReg();
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// The new opcode will clear the other half of the GR64 reg, so
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// cancel if that is live.
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unsigned thisSubRegIdx =
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(SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32
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: SystemZ::subreg_l32);
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unsigned otherSubRegIdx =
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(thisSubRegIdx == SystemZ::subreg_l32 ? SystemZ::subreg_h32
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: SystemZ::subreg_l32);
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unsigned GR64BitReg =
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TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass);
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Register OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);
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if (LiveRegs.contains(OtherReg))
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return false;
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uint64_t Imm = MI.getOperand(1).getImm();
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if (SystemZ::isImmLL(Imm)) {
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MI.setDesc(TII->get(LLIxL));
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MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
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return true;
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}
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if (SystemZ::isImmLH(Imm)) {
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MI.setDesc(TII->get(LLIxH));
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MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
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MI.getOperand(1).setImm(Imm >> 16);
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return true;
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}
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return false;
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}
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// Change MI's opcode to Opcode if register operand 0 has a 4-bit encoding.
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bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) {
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if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
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MI.setDesc(TII->get(Opcode));
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return true;
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}
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return false;
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}
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// Change MI's opcode to Opcode if register operands 0 and 1 have a
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// 4-bit encoding.
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bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) {
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if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
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SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
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MI.setDesc(TII->get(Opcode));
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return true;
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}
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return false;
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}
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// Change MI's opcode to Opcode if register operands 0, 1 and 2 have a
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// 4-bit encoding and if operands 0 and 1 are tied. Also ties op 0
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// with op 1, if MI becomes 2-address.
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bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
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if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
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MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
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SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
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MI.setDesc(TII->get(Opcode));
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tieOpsIfNeeded(MI);
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return true;
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}
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return false;
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}
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// Calls shortenOn001 if CCLive is false. CC def operand is added in
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// case of success.
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bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) {
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if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) {
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MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
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.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
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return true;
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}
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return false;
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}
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// MI is a vector-style conversion instruction with the operand order:
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// destination, source, exact-suppress, rounding-mode. If both registers
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// have a 4-bit encoding then change it to Opcode, which has operand order:
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// destination, rouding-mode, source, exact-suppress.
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bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {
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if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
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SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
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MachineOperand Dest(MI.getOperand(0));
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MachineOperand Src(MI.getOperand(1));
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MachineOperand Suppress(MI.getOperand(2));
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MachineOperand Mode(MI.getOperand(3));
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MI.RemoveOperand(3);
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MI.RemoveOperand(2);
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MI.RemoveOperand(1);
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MI.RemoveOperand(0);
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MI.setDesc(TII->get(Opcode));
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MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
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.add(Dest)
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.add(Mode)
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.add(Src)
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.add(Suppress);
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return true;
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}
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return false;
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}
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// MI is a three-operand select instruction. If one of the sources match
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// the destination, convert to the equivalent load-on-condition.
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bool SystemZShortenInst::shortenSelect(MachineInstr &MI, unsigned Opcode) {
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if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
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MI.setDesc(TII->get(Opcode));
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MI.tieOperands(0, 1);
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return true;
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}
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if (MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
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TII->commuteInstruction(MI, false, 1, 2);
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MI.setDesc(TII->get(Opcode));
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MI.tieOperands(0, 1);
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return true;
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}
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return false;
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}
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// Process all instructions in MBB. Return true if something changed.
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bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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// Set up the set of live registers at the end of MBB (live out)
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LiveRegs.clear();
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LiveRegs.addLiveOuts(MBB);
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// Iterate backwards through the block looking for instructions to change.
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for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
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MachineInstr &MI = *MBBI;
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switch (MI.getOpcode()) {
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case SystemZ::IILF:
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Changed |= shortenIIF(MI, SystemZ::LLILL, SystemZ::LLILH);
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break;
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case SystemZ::IIHF:
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Changed |= shortenIIF(MI, SystemZ::LLIHL, SystemZ::LLIHH);
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break;
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case SystemZ::SELR:
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Changed |= shortenSelect(MI, SystemZ::LOCR);
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break;
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case SystemZ::SELFHR:
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Changed |= shortenSelect(MI, SystemZ::LOCFHR);
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break;
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case SystemZ::SELGR:
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Changed |= shortenSelect(MI, SystemZ::LOCGR);
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break;
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case SystemZ::WFADB:
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Changed |= shortenOn001AddCC(MI, SystemZ::ADBR);
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break;
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case SystemZ::WFASB:
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Changed |= shortenOn001AddCC(MI, SystemZ::AEBR);
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break;
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case SystemZ::WFDDB:
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Changed |= shortenOn001(MI, SystemZ::DDBR);
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break;
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case SystemZ::WFDSB:
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Changed |= shortenOn001(MI, SystemZ::DEBR);
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break;
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case SystemZ::WFIDB:
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Changed |= shortenFPConv(MI, SystemZ::FIDBRA);
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break;
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case SystemZ::WFISB:
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Changed |= shortenFPConv(MI, SystemZ::FIEBRA);
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break;
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case SystemZ::WLDEB:
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Changed |= shortenOn01(MI, SystemZ::LDEBR);
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break;
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case SystemZ::WLEDB:
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Changed |= shortenFPConv(MI, SystemZ::LEDBRA);
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break;
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case SystemZ::WFMDB:
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Changed |= shortenOn001(MI, SystemZ::MDBR);
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break;
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case SystemZ::WFMSB:
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Changed |= shortenOn001(MI, SystemZ::MEEBR);
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break;
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case SystemZ::WFLCDB:
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Changed |= shortenOn01(MI, SystemZ::LCDFR);
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break;
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case SystemZ::WFLCSB:
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Changed |= shortenOn01(MI, SystemZ::LCDFR_32);
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break;
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case SystemZ::WFLNDB:
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Changed |= shortenOn01(MI, SystemZ::LNDFR);
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break;
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case SystemZ::WFLNSB:
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Changed |= shortenOn01(MI, SystemZ::LNDFR_32);
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break;
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case SystemZ::WFLPDB:
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Changed |= shortenOn01(MI, SystemZ::LPDFR);
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break;
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case SystemZ::WFLPSB:
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Changed |= shortenOn01(MI, SystemZ::LPDFR_32);
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break;
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case SystemZ::WFSQDB:
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Changed |= shortenOn01(MI, SystemZ::SQDBR);
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break;
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case SystemZ::WFSQSB:
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Changed |= shortenOn01(MI, SystemZ::SQEBR);
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break;
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case SystemZ::WFSDB:
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Changed |= shortenOn001AddCC(MI, SystemZ::SDBR);
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break;
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case SystemZ::WFSSB:
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Changed |= shortenOn001AddCC(MI, SystemZ::SEBR);
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break;
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case SystemZ::WFCDB:
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Changed |= shortenOn01(MI, SystemZ::CDBR);
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break;
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case SystemZ::WFCSB:
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Changed |= shortenOn01(MI, SystemZ::CEBR);
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break;
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case SystemZ::WFKDB:
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Changed |= shortenOn01(MI, SystemZ::KDBR);
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break;
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case SystemZ::WFKSB:
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Changed |= shortenOn01(MI, SystemZ::KEBR);
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break;
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case SystemZ::VL32:
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// For z13 we prefer LDE over LE to avoid partial register dependencies.
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Changed |= shortenOn0(MI, SystemZ::LDE32);
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break;
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case SystemZ::VST32:
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Changed |= shortenOn0(MI, SystemZ::STE);
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break;
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case SystemZ::VL64:
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Changed |= shortenOn0(MI, SystemZ::LD);
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break;
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case SystemZ::VST64:
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Changed |= shortenOn0(MI, SystemZ::STD);
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break;
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default: {
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int TwoOperandOpcode = SystemZ::getTwoOperandOpcode(MI.getOpcode());
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if (TwoOperandOpcode == -1)
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break;
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if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) &&
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(!MI.isCommutable() ||
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MI.getOperand(0).getReg() != MI.getOperand(2).getReg() ||
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!TII->commuteInstruction(MI, false, 1, 2)))
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break;
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MI.setDesc(TII->get(TwoOperandOpcode));
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MI.tieOperands(0, 1);
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if (TwoOperandOpcode == SystemZ::SLL ||
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TwoOperandOpcode == SystemZ::SLA ||
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TwoOperandOpcode == SystemZ::SRL ||
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TwoOperandOpcode == SystemZ::SRA) {
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// These shifts only use the low 6 bits of the shift count.
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MachineOperand &ImmMO = MI.getOperand(3);
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ImmMO.setImm(ImmMO.getImm() & 0xfff);
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}
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Changed = true;
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break;
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}
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}
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LiveRegs.stepBackward(MI);
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}
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return Changed;
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}
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bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) {
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if (skipFunction(F.getFunction()))
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return false;
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const SystemZSubtarget &ST = F.getSubtarget<SystemZSubtarget>();
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TII = ST.getInstrInfo();
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TRI = ST.getRegisterInfo();
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LiveRegs.init(*TRI);
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bool Changed = false;
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for (auto &MBB : F)
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Changed |= processBlock(MBB);
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return Changed;
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}
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