6dc5ba4cca
This reverts 0d3eee33f262402562a1ff28106dbb2f59031bdb and 4c37d30e22ae655394c8b3a7e292c06d393b9b44. XSfcie is not an official SiFive extension name. It stands for SiFive Custom Instruction Extension, which is mentioned in the S76 manual, but then elsewhere in the manual says it is not supported for S76. LLVM had various instructions and CSRs listed as part of this extension, but as far as SiFive is concerned, none of them are part of it. There are no documented extension names for these instructions and CSRs either externally or internally. If these are important to LLVM users, I can facilitate creating extension names for them and have them documented. For now I'm removing everything. Unfortunately, these instructions and CSRs are in LLVM 17 so this is an incompatible change.
609 lines
26 KiB
C++
609 lines
26 KiB
C++
//===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RISCVDisassembler class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "TargetInfo/RISCVTargetInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDecoderOps.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Endian.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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class RISCVDisassembler : public MCDisassembler {
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std::unique_ptr<MCInstrInfo const> const MCII;
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public:
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RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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MCInstrInfo const *MCII)
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: MCDisassembler(STI, Ctx), MCII(MCII) {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const override;
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private:
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void addSPOperands(MCInst &MI) const;
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};
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} // end anonymous namespace
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static MCDisassembler *createRISCVDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
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// Register the disassembler for each target.
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TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
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createRISCVDisassembler);
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TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
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createRISCVDisassembler);
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}
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static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureRVE);
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if (RegNo >= 32 || (IsRVE && RegNo >= 16))
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::X0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::F0_H + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::F0_F + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 8) {
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return MCDisassembler::Fail;
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}
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MCRegister Reg = RISCV::F8_F + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::F0_D + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 8) {
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return MCDisassembler::Fail;
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}
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MCRegister Reg = RISCV::F8_D + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo == 0) {
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return MCDisassembler::Fail;
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}
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return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus
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DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo == 2) {
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return MCDisassembler::Fail;
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}
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return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 8)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::X8 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32 || RegNo & 1)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::X0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= 8)
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return MCDisassembler::Fail;
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MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::V0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32 || RegNo % 2)
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return MCDisassembler::Fail;
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const RISCVDisassembler *Dis =
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static_cast<const RISCVDisassembler *>(Decoder);
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const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
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MCRegister Reg =
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RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
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&RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32 || RegNo % 4)
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return MCDisassembler::Fail;
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const RISCVDisassembler *Dis =
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static_cast<const RISCVDisassembler *>(Decoder);
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const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
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MCRegister Reg =
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RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
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&RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32 || RegNo % 8)
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return MCDisassembler::Fail;
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const RISCVDisassembler *Dis =
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static_cast<const RISCVDisassembler *>(Decoder);
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const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
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MCRegister Reg =
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RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
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&RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo > 2) {
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return MCDisassembler::Fail;
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}
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MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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template <unsigned N>
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static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template <unsigned N>
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static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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if (Imm == 0)
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return MCDisassembler::Fail;
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return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
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}
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template <unsigned N>
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static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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// Sign-extend the number in the bottom N bits of Imm
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Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
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return MCDisassembler::Success;
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}
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template <unsigned N>
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static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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if (Imm == 0)
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return MCDisassembler::Fail;
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return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
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}
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template <unsigned N>
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static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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// Sign-extend the number in the bottom N bits of Imm after accounting for
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// the fact that the N bit immediate is stored in N-1 bits (the LSB is
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// always zero)
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Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<6>(Imm) && "Invalid immediate");
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if (Imm > 31) {
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Imm = (SignExtend64<6>(Imm) & 0xfffff);
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}
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<3>(Imm) && "Invalid immediate");
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if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm,
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uint64_t Address, const void *Decoder);
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static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
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uint64_t Address, const void *Decoder);
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#include "RISCVGenDisassemblerTables.inc"
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static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
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DecodeStatus Result = DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder);
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(void)Result;
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assert(Result == MCDisassembler::Success && "Invalid register");
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Inst.addOperand(Inst.getOperand(0));
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Inst.addOperand(MCOperand::createImm(0));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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Inst.addOperand(MCOperand::createReg(RISCV::X0));
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uint32_t SImm6 =
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fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
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DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
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(void)Result;
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assert(Result == MCDisassembler::Success && "Invalid immediate");
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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Inst.addOperand(MCOperand::createReg(RISCV::X0));
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Inst.addOperand(Inst.getOperand(0));
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uint32_t UImm6 =
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fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
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DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
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(void)Result;
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assert(Result == MCDisassembler::Success && "Invalid immediate");
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
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uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
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DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
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DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
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uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
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DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
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Inst.addOperand(Inst.getOperand(0));
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DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5);
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uint32_t Rs1 = fieldFromInstruction(Insn, 15, 5);
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uint32_t Rd2 = fieldFromInstruction(Insn, 20, 5);
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uint32_t UImm2 = fieldFromInstruction(Insn, 25, 2);
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DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder);
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DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder);
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DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
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DecodeStatus Result = decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
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(void)Result;
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assert(Result == MCDisassembler::Success && "Invalid immediate");
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// Disassemble the final operand which is implicit.
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unsigned Opcode = Inst.getOpcode();
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bool IsWordOp = (Opcode == RISCV::TH_LWD || Opcode == RISCV::TH_LWUD ||
|
|
Opcode == RISCV::TH_SWD);
|
|
if (IsWordOp)
|
|
Inst.addOperand(MCOperand::createImm(3));
|
|
else
|
|
Inst.addOperand(MCOperand::createImm(4));
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm,
|
|
uint64_t Address, const void *Decoder) {
|
|
if (Imm <= 3)
|
|
return MCDisassembler::Fail;
|
|
Inst.addOperand(MCOperand::createImm(Imm));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
uint32_t Rs1 = fieldFromInstruction(Insn, 0, 5);
|
|
uint32_t Rs2 = fieldFromInstruction(Insn, 5, 5);
|
|
DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
|
|
DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
|
|
uint64_t Address, const void *Decoder) {
|
|
Inst.addOperand(MCOperand::createImm(Imm));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
// Add implied SP operand for C.*SP compressed instructions. The SP operand
|
|
// isn't explicitly encoded in the instruction.
|
|
void RISCVDisassembler::addSPOperands(MCInst &MI) const {
|
|
const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
|
|
for (unsigned i = 0; i < MCID.getNumOperands(); i++)
|
|
if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
|
|
MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
|
|
}
|
|
|
|
DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
|
|
ArrayRef<uint8_t> Bytes,
|
|
uint64_t Address,
|
|
raw_ostream &CS) const {
|
|
// TODO: This will need modification when supporting instruction set
|
|
// extensions with instructions > 32-bits (up to 176 bits wide).
|
|
uint32_t Insn;
|
|
DecodeStatus Result;
|
|
|
|
#define TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, \
|
|
DESC, ADDITIONAL_OPERATION) \
|
|
do { \
|
|
if (FEATURE_CHECKS) { \
|
|
LLVM_DEBUG(dbgs() << "Trying " DESC ":\n"); \
|
|
Result = decodeInstruction(DECODER_TABLE, MI, Insn, Address, this, STI); \
|
|
if (Result != MCDisassembler::Fail) { \
|
|
ADDITIONAL_OPERATION; \
|
|
return Result; \
|
|
} \
|
|
} \
|
|
} while (false)
|
|
#define TRY_TO_DECODE_AND_ADD_SP(FEATURE_CHECKS, DECODER_TABLE, DESC) \
|
|
TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, DESC, \
|
|
addSPOperands(MI))
|
|
#define TRY_TO_DECODE(FEATURE_CHECKS, DECODER_TABLE, DESC) \
|
|
TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, DESC, \
|
|
(void)nullptr)
|
|
#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC) \
|
|
TRY_TO_DECODE(STI.hasFeature(FEATURE), DECODER_TABLE, DESC)
|
|
|
|
// It's a 32 bit instruction if bit 0 and 1 are 1.
|
|
if ((Bytes[0] & 0x3) == 0x3) {
|
|
if (Bytes.size() < 4) {
|
|
Size = 0;
|
|
return MCDisassembler::Fail;
|
|
}
|
|
Size = 4;
|
|
|
|
Insn = support::endian::read32le(Bytes.data());
|
|
|
|
TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
|
|
!STI.hasFeature(RISCV::Feature64Bit),
|
|
DecoderTableRV32Zdinx32,
|
|
"RV32Zdinx table (Double in Integer and rv32)");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
|
|
"RVZfinx table (Float in Integer)");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps,
|
|
DecoderTableXVentana32, "Ventana custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
|
|
"XTHeadBa custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32,
|
|
"XTHeadBb custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32,
|
|
"XTHeadBs custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCondMov,
|
|
DecoderTableXTHeadCondMov32,
|
|
"XTHeadCondMov custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32,
|
|
"XTHeadCmo custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadFMemIdx,
|
|
DecoderTableXTHeadFMemIdx32,
|
|
"XTHeadFMemIdx custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32,
|
|
"XTHeadMac custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemIdx,
|
|
DecoderTableXTHeadMemIdx32,
|
|
"XTHeadMemIdx custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemPair,
|
|
DecoderTableXTHeadMemPair32,
|
|
"XTHeadMemPair custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync,
|
|
DecoderTableXTHeadSync32,
|
|
"XTHeadSync custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableXTHeadVdot32,
|
|
"XTHeadVdot custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
|
|
"SiFive VCIX custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(
|
|
RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32,
|
|
"SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table");
|
|
TRY_TO_DECODE_FEATURE(
|
|
RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32,
|
|
"SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table");
|
|
TRY_TO_DECODE_FEATURE(
|
|
RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
|
|
"SiFive Matrix Multiplication Instruction opcode table");
|
|
TRY_TO_DECODE_FEATURE(
|
|
RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
|
|
"SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
|
|
DecoderTableXCVbitmanip32,
|
|
"CORE-V Bit Manipulation custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
|
|
"CORE-V Event load custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
|
|
"CORE-V MAC custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
|
|
"CORE-V MEM custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
|
|
"CORE-V ALU custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
|
|
"CORE-V SIMD extensions custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
|
|
"CORE-V Immediate Branching custom opcode table");
|
|
TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
|
|
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
if (Bytes.size() < 2) {
|
|
Size = 0;
|
|
return MCDisassembler::Fail;
|
|
}
|
|
Size = 2;
|
|
|
|
Insn = support::endian::read16le(Bytes.data());
|
|
TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit),
|
|
DecoderTableRISCV32Only_16,
|
|
"RISCV32Only_16 table (16-bit Instruction)");
|
|
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZcmt, DecoderTableRVZcmt16,
|
|
"Zcmt table (16-bit Table Jump Instructions)");
|
|
TRY_TO_DECODE_FEATURE(
|
|
RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
|
|
"Zcmp table (16-bit Push/Pop & Double Move Instructions)");
|
|
TRY_TO_DECODE_AND_ADD_SP(true, DecoderTable16,
|
|
"RISCV_C table (16-bit Instruction)");
|
|
|
|
return MCDisassembler::Fail;
|
|
}
|