dba54fb074
It constrains vector registers excluding v0. Refer to https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html RISC-V part. This patch also adds a testcase for constraints vr, vd and vm.
47 lines
1.5 KiB
C
47 lines
1.5 KiB
C
// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv32 -target-feature +v \
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// RUN: -O2 -emit-llvm %s -o - \
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// RUN: | FileCheck %s
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// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
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// RUN: -O2 -emit-llvm %s -o - \
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// RUN: | FileCheck %s
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// Test RISC-V V-extension specific inline assembly constraints.
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#include <riscv_vector.h>
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void test_v_reg() {
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asm volatile(
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"vsetvli x1, x0, e32,m2,tu,mu\n"
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"vadd.vv v1, v2, v3, v0.t"
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:
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:
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: "v1", "x1");
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// CHECK-LABEL: define{{.*}} @test_v_reg
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// CHECK: "~{v1},~{x1}"
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}
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vint32m1_t test_vr(vint32m1_t a, vint32m1_t b) {
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// CHECK-LABEL: define{{.*}} @test_vr
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// CHECK: %0 = tail call <vscale x 2 x i32> asm sideeffect "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
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vint32m1_t ret;
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asm volatile ("vadd.vv %0, %1, %2" : "=vr"(ret) : "vr"(a), "vr"(b));
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return ret;
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}
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vint32m1_t test_vd(vint32m1_t a, vint32m1_t b) {
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// CHECK-LABEL: define{{.*}} @test_vd
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// CHECK: %0 = tail call <vscale x 2 x i32> asm sideeffect "vadd.vv $0, $1, $2", "=^vd,^vd,^vd"(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
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vint32m1_t ret;
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asm volatile ("vadd.vv %0, %1, %2" : "=vd"(ret) : "vd"(a), "vd"(b));
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return ret;
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}
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vbool1_t test_vm(vbool1_t a, vbool1_t b) {
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// CHECK-LABEL: define{{.*}} @test_vm
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// CHECK: %0 = tail call <vscale x 64 x i1> asm sideeffect "vmand.mm $0, $1, $2", "=^vm,^vm,^vm"(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b)
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vbool1_t ret;
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asm volatile ("vmand.mm %0, %1, %2" : "=vm"(ret) : "vm"(a), "vm"(b));
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return ret;
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}
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