b021464d35
Update VPlan to include the scalar loop header. This allows retiring VPLiveOut, as the remaining live-outs can now be handled by adding operands to the wrapped phis in the scalar loop header. Note that the current version only includes the scalar loop header, no other loop blocks and also does not wrap it in a region block. PR: https://github.com/llvm/llvm-project/pull/109975
129 lines
5.1 KiB
LLVM
129 lines
5.1 KiB
LLVM
; RUN: opt -passes=loop-vectorize -force-vector-width=8 -force-vector-interleave=2 -disable-output -debug -S %s 2>&1 | FileCheck --check-prefixes=CHECK %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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; REQUIRES: asserts
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; Check if the vector loop condition can be simplified to true for a given
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; VF/IC combination.
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define void @test_tc_less_than_16(ptr %A, i64 %N) {
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; CHECK: LV: Scalarizing: %cmp =
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; CHECK: VPlan 'Initial VPlan for VF={8},UF>=1' {
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; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF
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; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count
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; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<entry>:
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; CHECK-NEXT: IR %and = and i64 %N, 15
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; CHECK-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV (zext i4 (trunc i64 %N to i4) to i64)
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; CHECK-NEXT: No successors
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; CHECK-EMPTY:
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; CHECK-NEXT: vector.ph:
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; CHECK-NEXT: Successor(s): vector loop
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; CHECK-EMPTY:
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; CHECK-NEXT: <x1> vector loop: {
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; CHECK-NEXT: vector.body:
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; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
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; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
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; CHECK-NEXT: EMIT vp<[[PADD:%.+]]> = ptradd ir<%A>, vp<[[STEPS]]>
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; CHECK-NEXT: vp<[[VPTR:%.]]> = vector-pointer vp<[[PADD]]>
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; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VPTR]]>
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; CHECK-NEXT: WIDEN ir<%add> = add nsw ir<%l>, ir<10>
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; CHECK-NEXT: vp<[[VPTR2:%.+]]> = vector-pointer vp<[[PADD]]>
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; CHECK-NEXT: WIDEN store vp<[[VPTR2]]>, ir<%add>
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; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV:%.+]]>, vp<[[VFxUF]]>
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; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): middle.block
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; CHECK-EMPTY:
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; CHECK-NEXT: middle.block:
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; CHECK-NEXT: EMIT vp<[[C:%.+]]> = icmp eq vp<[[TC]]>, vp<[[VTC]]>
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; CHECK-NEXT: EMIT branch-on-cond vp<[[C]]>
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; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<exit>:
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; CHECK-NEXT: No successors
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; CHECK-EMPTY:
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; CHECK-NEXT: scalar.ph:
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; CHECK-NEXT: Successor(s): ir-bb<loop>
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<loop>:
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; CHECK-NEXT: IR %iv = phi i64 [ %and, %entry ], [ %iv.next, %loop ]
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; CHECK-NEXT: IR %p.src = phi ptr [ %A, %entry ], [ %p.src.next, %loop ]
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; CHECK: IR %cmp = icmp eq i64 %iv.next, 0
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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;
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; CHECK: Executing best plan with VF=8, UF=2
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; CHECK-NEXT: VPlan 'Final VPlan for VF={8},UF={2}' {
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; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF
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; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count
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; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<entry>:
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; CHECK-NEXT: IR %and = and i64 %N, 15
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; CHECK-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV (zext i4 (trunc i64 %N to i4) to i64)
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; CHECK-NEXT: No successors
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; CHECK-EMPTY:
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; CHECK-NEXT: vector.ph:
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; CHECK-NEXT: Successor(s): vector loop
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; CHECK-EMPTY:
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; CHECK-NEXT: <x1> vector loop: {
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; CHECK-NEXT: vector.body:
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; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
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; CHECK-NEXT: vp<[[STEPS1:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
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; CHECK-NEXT: EMIT vp<[[PADD1:%.+]]> = ptradd ir<%A>, vp<[[STEPS1]]>
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; CHECK-NEXT: vp<[[VPTR1:%.]]> = vector-pointer vp<[[PADD1]]>
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; CHECK-NEXT: vp<[[VPTR2:%.]]> = vector-pointer vp<[[PADD1]]>, ir<1>
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; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VPTR1]]>
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; CHECK-NEXT: WIDEN ir<%l>.1 = load vp<[[VPTR2]]>
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; CHECK-NEXT: WIDEN ir<%add> = add nsw ir<%l>, ir<10>
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; CHECK-NEXT: WIDEN ir<%add>.1 = add nsw ir<%l>.1, ir<10>
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; CHECK-NEXT: vp<[[VPTR3:%.+]]> = vector-pointer vp<[[PADD1]]>
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; CHECK-NEXT: vp<[[VPTR4:%.+]]> = vector-pointer vp<[[PADD1]]>, ir<1>
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; CHECK-NEXT: WIDEN store vp<[[VPTR3]]>, ir<%add>
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; CHECK-NEXT: WIDEN store vp<[[VPTR4]]>, ir<%add>.1
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; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV:%.+]]>, vp<[[VFxUF]]>
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; CHECK-NEXT: EMIT branch-on-cond ir<true>
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): middle.block
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; CHECK-EMPTY:
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; CHECK-NEXT: middle.block:
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; CHECK-NEXT: EMIT vp<[[C:%.+]]> = icmp eq vp<[[TC]]>, vp<[[VTC]]>
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; CHECK-NEXT: EMIT branch-on-cond vp<[[C]]>
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; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<exit>:
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; CHECK-NEXT: No successors
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; CHECK-EMPTY:
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; CHECK-NEXT: scalar.ph:
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; CHECK-NEXT: Successor(s): ir-bb<loop>
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<loop>:
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; CHECK-NEXT: IR %iv = phi i64 [ %and, %entry ], [ %iv.next, %loop ]
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; CHECK-NEXT: IR %p.src = phi ptr [ %A, %entry ], [ %p.src.next, %loop ]
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; CHECK: IR %cmp = icmp eq i64 %iv.next, 0
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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;
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entry:
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%and = and i64 %N, 15
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br label %loop
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loop:
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%iv = phi i64 [ %and, %entry ], [ %iv.next, %loop ]
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%p.src = phi ptr [ %A, %entry ], [ %p.src.next, %loop ]
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%p.src.next = getelementptr inbounds i8, ptr %p.src, i64 1
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%l = load i8, ptr %p.src, align 1
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%add = add nsw i8 %l, 10
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store i8 %add, ptr %p.src
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%iv.next = add nsw i64 %iv, -1
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%cmp = icmp eq i64 %iv.next, 0
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br i1 %cmp, label %exit, label %loop
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exit:
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ret void
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}
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