3f2ed812f0
Builds on #67982 which recently introduced the nneg flag on a zext instruction. InstCombine is one of our largest canonicalizers of zext from non-negative sext instructions, so set the flag there.
78 lines
3.4 KiB
LLVM
78 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
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; RUN: opt -mtriple=amdgcn-- -passes='default<O3>' -S %s | FileCheck %s
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; Check that loop unswitch happened and condition hoisted out of the loop.
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; Condition is uniform so even targets with divergence should perform unswitching.
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; This fails with the new pass manager:
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; https://bugs.llvm.org/show_bug.cgi?id=48819
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; The correct behaviour (allow uniform non-trivial branches to be
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; unswitched on all targets) requires access to the function-level
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; divergence analysis from a loop transform, which is currently not
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; supported in the new pass manager.
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; SHOULDBE-LABEL: {{^}}define amdgpu_kernel void @uniform_unswitch
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; SHOULDBE: entry:
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; SHOULDBE-NEXT: [[LOOP_COND:%[a-z0-9]+]] = icmp
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; SHOULDBE-NEXT: [[IF_COND:%[a-z0-9]+]] = icmp eq i32 %x, 123456
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; SHOULDBE-NEXT: and i1 [[LOOP_COND]], [[IF_COND]]
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; SHOULDBE-NEXT: br i1
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define amdgpu_kernel void @uniform_unswitch(ptr nocapture %out, i32 %n, i32 %x) {
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; CHECK-LABEL: define amdgpu_kernel void @uniform_unswitch(
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; CHECK-SAME: ptr nocapture writeonly [[OUT:%.*]], i32 [[N:%.*]], i32 [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[OUT_GLOBAL:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(1)
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; CHECK-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[N]], 0
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; CHECK-NEXT: br i1 [[CMP6]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
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; CHECK: for.body.lr.ph:
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[X]], 123456
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: ret void
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; CHECK: for.body:
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; CHECK-NEXT: [[I_07:%.*]] = phi i32 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[FOR_INC:%.*]] ]
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; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]]
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; CHECK: if.then:
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; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[I_07]] to i64
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[OUT_GLOBAL]], i64 [[TMP0]]
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; CHECK-NEXT: store i32 [[I_07]], ptr addrspace(1) [[ARRAYIDX]], align 4
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; CHECK-NEXT: br label [[FOR_INC]]
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; CHECK: for.inc:
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; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_07]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
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;
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entry:
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%cmp6 = icmp sgt i32 %n, 0
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br i1 %cmp6, label %for.body.lr.ph, label %for.cond.cleanup
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for.body.lr.ph: ; preds = %entry
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%cmp1 = icmp eq i32 %x, 123456
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br label %for.body
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for.cond.cleanup.loopexit: ; preds = %for.inc
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry
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ret void
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for.body: ; preds = %for.inc, %for.body.lr.ph
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%i.07 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.inc ]
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br i1 %cmp1, label %if.then, label %for.inc
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if.then: ; preds = %for.body
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%arrayidx = getelementptr inbounds i32, ptr %out, i32 %i.07
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store i32 %i.07, ptr %arrayidx, align 4
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br label %for.inc
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for.inc: ; preds = %for.body, %if.then
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%inc = add nuw nsw i32 %i.07, 1
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%exitcond = icmp eq i32 %inc, %n
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br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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