64ed699b3d
When the default branch is the last case, we can transform that branch
into a concrete branch with an unreachable default branch.
```llvm
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define i64 @src(i64 %0) {
%2 = urem i64 %0, 4
switch i64 %2, label %5 [
i64 1, label %3
i64 2, label %3
i64 3, label %4
]
3: ; preds = %1, %1
br label %5
4: ; preds = %1
br label %5
5: ; preds = %1, %4, %3
%.0 = phi i64 [ 2, %4 ], [ 1, %3 ], [ 0, %1 ]
ret i64 %.0
}
define i64 @tgt(i64 %0) {
%2 = urem i64 %0, 4
switch i64 %2, label %unreachable [
i64 0, label %5
i64 1, label %3
i64 2, label %3
i64 3, label %4
]
unreachable: ; preds = %1
unreachable
3: ; preds = %1, %1
br label %5
4: ; preds = %1
br label %5
5: ; preds = %1, %4, %3
%.0 = phi i64 [ 2, %4 ], [ 1, %3 ], [ 0, %1 ]
ret i64 %.0
}
```
Alive2: https://alive2.llvm.org/ce/z/Y-PGXv
After transform to a lookup table, I believe `tgt` is better code.
The final instructions are as follows:
```asm
src: # @src
and edi, 3
lea rax, [rdi - 1]
cmp rax, 2
ja .LBB0_1
mov rax, qword ptr [8*rdi + .Lswitch.table.src-8]
ret
.LBB0_1:
xor eax, eax
ret
tgt: # @tgt
and edi, 3
mov rax, qword ptr [8*rdi + .Lswitch.table.tgt]
ret
.Lswitch.table.src:
.quad 1 # 0x1
.quad 1 # 0x1
.quad 2 # 0x2
.Lswitch.table.tgt:
.quad 0 # 0x0
.quad 1 # 0x1
.quad 1 # 0x1
.quad 2 # 0x2
```
Godbolt: https://llvm.godbolt.org/z/borME8znd
Closes #73446.
(cherry picked from commit 7d81e072712f4e6a150561b5538ccebda289aa13)
62 lines
1.4 KiB
LLVM
62 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt %s -S -passes='simplifycfg<switch-to-lookup>' -simplifycfg-require-and-preserve-domtree=1 -switch-range-to-icmp | FileCheck %s
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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define i64 @test_1(i64 %0) {
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; CHECK-LABEL: define i64 @test_1(
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; CHECK-SAME: i64 [[TMP0:%.*]]) {
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; CHECK-NEXT: switch.lookup:
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; CHECK-NEXT: [[TMP1:%.*]] = urem i64 [[TMP0]], 4
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; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i64], ptr @switch.table.test_1, i32 0, i64 [[TMP1]]
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; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i64, ptr [[SWITCH_GEP]], align 8
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; CHECK-NEXT: ret i64 [[SWITCH_LOAD]]
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;
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%2 = urem i64 %0, 4
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switch i64 %2, label %5 [
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i64 1, label %3
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i64 2, label %3
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i64 3, label %4
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]
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3:
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br label %5
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4:
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br label %5
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5:
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%.0 = phi i64 [ 2, %4 ], [ 1, %3 ], [ 0, %1 ]
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ret i64 %.0
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}
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define i64 @test_2(i64 %0) {
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; CHECK-LABEL: define i64 @test_2(
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; CHECK-SAME: i64 [[TMP0:%.*]]) {
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; CHECK-NEXT: switch.lookup:
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; CHECK-NEXT: [[TMP1:%.*]] = urem i64 [[TMP0]], 4
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; CHECK-NEXT: ret i64 [[TMP1]]
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;
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%2 = urem i64 %0, 4
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switch i64 %2, label %6 [
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i64 1, label %3
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i64 2, label %4
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i64 3, label %5
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]
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3:
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br label %6
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4:
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br label %6
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5:
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br label %6
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6:
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%.0 = phi i64 [ 0, %1 ], [ 1, %3 ], [ 2, %4 ], [ 3, %5 ]
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ret i64 %.0
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}
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