c5e6c886aa
The generic implementation is umin(TC, VF * vscale). Lowering to vsetvli for RISC-V will come in a future patch. This patch is a pre-requisite to be able to CodeGen vectorized code from D99750. Reviewed By: reames, frasercrmck Differential Revision: https://reviews.llvm.org/D149916
18 lines
725 B
LLVM
18 lines
725 B
LLVM
; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
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declare i32 @llvm.experimental.get.vector.length.i32(i32, i32, i1)
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define i32 @vector_length_negative_vf(i32 zeroext %tc) {
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; CHECK: get_vector_length: VF must be positive
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; CHECK-NEXT: %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 -1, i1 true)
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%a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 -1, i1 true)
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ret i32 %a
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}
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define i32 @vector_length_zero_vf(i32 zeroext %tc) {
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; CHECK: get_vector_length: VF must be positive
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; CHECK-NEXT: %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 0, i1 true)
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%a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 0, i1 true)
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ret i32 %a
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}
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