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llvm-project/llvm/lib/Target/RISCV
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luxufan 6c5039a10f [RISCV] add the assemble and disassemble support of Zvlsseg instructions 
This implements the assemble and disassemble support of RISCV Vector
extension Zvlsseg instructions, base on the 0.9 spec version.

Reviewed  by HsiangKai

Differential Revision: https://reviews.llvm.org/D84416
2020-08-19 16:22:25 +08:00
..
AsmParser
Upgrade MC to v0.9.
2020-08-01 07:42:06 +08:00
Disassembler
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
MCTargetDesc
[X86][MC][Target] Initial backend support a tune CPU to support -mtune
2020-08-14 15:31:50 -07:00
TargetInfo
CMake: Make most target symbols hidden by default
2020-01-14 19:46:52 -08:00
Utils
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
CMakeLists.txt
[RISCV] Split the pseudo instruction splitting pass
2020-06-29 14:35:57 +01:00
LLVMBuild.txt
…
RISCV.h
[RISCV] Split the pseudo instruction splitting pass
2020-06-29 14:35:57 +01:00
RISCV.td
[RISCV] add the assemble and disassemble support of Zvlsseg instructions
2020-08-19 16:22:25 +08:00
RISCVAsmPrinter.cpp
[RISCV] ELF attribute section for RISC-V.
2020-03-31 16:16:19 +08:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
2020-07-15 10:50:55 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
2020-07-15 10:50:55 +01:00
RISCVFrameLowering.cpp
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
2020-07-01 07:28:11 +00:00
RISCVFrameLowering.h
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
RISCVInstrFormats.td
Upgrade MC to v0.9.
2020-08-01 07:42:06 +08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
Upgrade MC to v0.9.
2020-08-01 07:42:06 +08:00
RISCVInstrInfo.cpp
[RISCV] Indirect branch generation in position independent code
2020-08-17 13:09:26 +01:00
RISCVInstrInfo.h
Upgrade MC to v0.9.
2020-08-01 07:42:06 +08:00
RISCVInstrInfo.td
[RISCV] Indirect branch generation in position independent code
2020-08-17 13:09:26 +01:00
RISCVInstrInfoA.td
RISCV: Avoid GlobalISel build break in a future patch
2020-07-13 14:01:57 -04:00
RISCVInstrInfoB.td
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions
2020-07-15 12:19:34 +01:00
RISCVInstrInfoC.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrInfoD.td
[RISCV] Add patterns for checking isnan
2020-05-02 15:01:04 +01:00
RISCVInstrInfoF.td
[RISCV] Add patterns for checking isnan
2020-05-02 15:01:04 +01:00
RISCVInstrInfoM.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrInfoV.td
[RISCV] add the assemble and disassemble support of Zvlsseg instructions
2020-08-19 16:22:25 +08:00
RISCVInstructionSelector.cpp
RISCV: Avoid GlobalISel build break in a future patch
2020-07-13 14:01:57 -04:00
RISCVISelDAGToDAG.cpp
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions
2020-07-15 12:19:34 +01:00
RISCVISelDAGToDAG.h
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions
2020-07-15 12:19:34 +01:00
RISCVISelLowering.cpp
[RISCV] eliminate the repetition declare of SDLoc DL
2020-08-03 10:24:30 +08:00
RISCVISelLowering.h
[RISCV] Optimize multiplication by constant
2020-07-07 18:50:24 -07:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.h
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
2020-07-01 07:28:11 +00:00
RISCVMCInstLower.cpp
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
2020-07-14 11:15:01 +01:00
RISCVMergeBaseOffset.cpp
…
RISCVRegisterBankInfo.cpp
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBankInfo.h
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
RISCV: Don't store function in RISCVMachineFunctionInfo
2020-06-30 16:08:51 -04:00
RISCVRegisterInfo.h
CodeGen: More conversions to use Register
2020-04-07 18:54:36 -04:00
RISCVRegisterInfo.td
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
RISCVSchedRocket32.td
[RISCV] add the assemble and disassemble support of Zvlsseg instructions
2020-08-19 16:22:25 +08:00
RISCVSchedRocket64.td
[RISCV] add the assemble and disassemble support of Zvlsseg instructions
2020-08-19 16:22:25 +08:00
RISCVSchedule.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVSubtarget.cpp
[X86][MC][Target] Initial backend support a tune CPU to support -mtune
2020-08-14 15:31:50 -07:00
RISCVSubtarget.h
[RISCV] add the assemble and disassemble support of Zvlsseg instructions
2020-08-19 16:22:25 +08:00
RISCVSystemOperands.td
[RISCV] Enable the use of the old mucounteren name
2020-08-17 13:11:49 +01:00
RISCVTargetMachine.cpp
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
2020-07-14 11:15:01 +01:00
RISCVTargetMachine.h
[RISCV] Add subtargets initialized with target feature
2019-12-17 09:34:01 -08:00
RISCVTargetObjectFile.cpp
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
2020-05-21 15:23:29 -07:00
RISCVTargetObjectFile.h
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
2020-05-21 15:23:29 -07:00
RISCVTargetTransformInfo.cpp
[NFC][CostModel] Add TargetCostKind to relevant APIs
2020-05-05 10:35:54 +01:00
RISCVTargetTransformInfo.h
[NFC][CostModel] Add TargetCostKind to relevant APIs
2020-05-05 10:35:54 +01:00