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llvm-project/llvm/lib/Target/AArch64
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David Blaikie b627802e81 Remove unused variable (rolling it into an assert)
2021-03-09 16:06:44 -08:00
..
AsmParser
[AArch64AsmParser] Fix type-limits warning for VectorIndex.
2021-02-08 15:35:30 +00:00
Disassembler
[AArch64] Adding the v8.7-A LD64B/ST64B Accelerator extension
2020-12-17 13:46:23 +00:00
GISel
Remove unused variable (rolling it into an assert)
2021-03-09 16:06:44 -08:00
MCTargetDesc
[MC][AArch64] Support .reloc *, BFD_RELOC_{NONE,16,32,64}, *
2021-03-05 21:31:08 -08:00
TargetInfo
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
Utils
[ARM][AArch64] Adding basic support for the v8.7-A architecture
2020-12-17 13:45:08 +00:00
AArch64.h
[AArch64] Homogeneous Prolog and Epilog Size Optimization
2021-02-02 14:57:26 -08:00
AArch64.td
[AArch64] Add some missing Neoverse features
2021-02-19 09:18:35 +00:00
AArch64A53Fix835769.cpp
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AArch64A57FPLoadBalancing.cpp
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AArch64AdvSIMDScalarPass.cpp
[AArch64] Update a code comment incorrectly referring to zero_reg. NFC
2020-08-20 14:36:59 +02:00
AArch64AsmPrinter.cpp
Reapply "[DebugInfo] Add new instruction and DIExpression operator for variadic debug values"
2021-03-05 12:32:05 +00:00
AArch64BranchTargets.cpp
[AArch64] PAC/BTI code generation for LLVM generated functions
2020-09-25 11:47:14 +01:00
AArch64CallingConvention.cpp
[SVE] Deal with SVE tuple call arguments correctly when running out of registers
2020-11-12 08:41:50 +00:00
AArch64CallingConvention.h
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AArch64CallingConvention.td
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AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp
[AArch64] Fix emitting an AdrpAddLdr LOH when there's a potential clobber of the
2021-03-01 13:52:57 -08:00
AArch64Combine.td
[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP
2021-03-08 13:01:10 -08:00
AArch64CompressJumpTables.cpp
[AArch64] Don't try to compress jump tables if there are any inline asm instructions.
2020-12-10 12:20:02 -08:00
AArch64CondBrTuning.cpp
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AArch64ConditionalCompares.cpp
DomTree: Remove getChildren() accessor
2020-07-06 21:58:11 +02:00
AArch64ConditionOptimizer.cpp
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AArch64DeadRegisterDefinitionsPass.cpp
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AArch64ExpandImm.cpp
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AArch64ExpandImm.h
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AArch64ExpandPseudoInsts.cpp
[AArch64] Add implicit uses for operands when expanding BLR_RVMARKER.
2021-03-03 21:56:05 +00:00
AArch64FalkorHWPFFix.cpp
Small fixes for "[LoopInfo] empty() -> isInnermost(), add isOutermost()"
2020-09-22 23:59:34 +03:00
AArch64FastISel.cpp
AArch64: relax address-space assertion in FastISel.
2021-02-25 10:15:55 +00:00
AArch64FrameLowering.cpp
[ARM] Add comment explaining stack frame layout
2021-03-09 15:20:32 +00:00
AArch64FrameLowering.h
[AArch64] Homogeneous Prolog and Epilog Size Optimization
2021-02-02 14:57:26 -08:00
AArch64GenRegisterBankInfo.def
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AArch64InstrAtomics.td
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AArch64InstrFormats.td
[CodeGen] Fix issues with subvector intrinsic index types
2021-03-01 10:28:21 +00:00
AArch64InstrGISel.td
[AArch64][GlobalISel] Add selection support for fpr bank source variants of G_SITOFP and G_UITOFP.
2021-01-14 19:31:19 -08:00
AArch64InstrInfo.cpp
[GlobalISel] Propagate extends through G_PHIs into the incoming value blocks.
2021-02-12 11:52:52 -08:00
AArch64InstrInfo.h
[GlobalISel] Propagate extends through G_PHIs into the incoming value blocks.
2021-02-12 11:52:52 -08:00
AArch64InstrInfo.td
[AArch64] Add missing intrinsics for vrnd
2021-03-05 11:26:12 +00:00
AArch64ISelDAGToDAG.cpp
[AArch64] Adding ACLE intrinsics for the LS64 extension
2021-01-14 09:43:58 +00:00
AArch64ISelLowering.cpp
[IR] Introduce llvm.experimental.vector.splice intrinsic
2021-03-09 10:44:22 +00:00
AArch64ISelLowering.h
[AArch64] Move CALL_RVMARKER definition after CALL.
2021-03-03 19:42:16 +00:00
AArch64LoadStoreOptimizer.cpp
[AArch64] Do not fold SP adjustments into pre-increment addr modes if it overflows the redzone.
2021-02-24 09:55:48 -08:00
AArch64LowerHomogeneousPrologEpilog.cpp
AArch64LowerHomogeneousPrologEpilog.cpp - fix Wdocumentation warning. NFCI.
2021-02-05 11:34:43 +00:00
AArch64MachineFunctionInfo.cpp
[AArch64] PAC/BTI code generation for LLVM generated functions
2020-09-25 11:47:14 +01:00
AArch64MachineFunctionInfo.h
[AArch64][SVE] Allow accesses to SVE stack objects to use frame pointer
2021-01-28 12:39:57 +00:00
AArch64MacroFusion.cpp
[AArch64] Add Cortex CPU subtarget features for instruction fusion.
2021-01-25 09:11:29 +00:00
AArch64MacroFusion.h
[llvm] Add missing header guards (NFC)
2021-01-30 09:53:42 -08:00
AArch64MCInstLower.cpp
[AArch64] [Windows] Properly add :lo12: reloc specifiers when generating assembly
2021-01-12 23:56:03 +02:00
AArch64MCInstLower.h
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AArch64PBQPRegAlloc.cpp
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AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PfmCounters.td
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AArch64PromoteConstant.cpp
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AArch64RedundantCopyElimination.cpp
[AArch64] Fix Copy Elemination for negative values
2020-12-18 13:30:46 +00:00
AArch64RegisterBanks.td
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AArch64RegisterInfo.cpp
Change materializeFrameBaseRegister() to return register
2021-01-22 15:51:06 -08:00
AArch64RegisterInfo.h
Change materializeFrameBaseRegister() to return register
2021-01-22 15:51:06 -08:00
AArch64RegisterInfo.td
[AArch64] Add a GPR64x8 register class
2020-12-17 13:45:46 +00:00
AArch64SchedA53.td
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AArch64SchedA55.td
[MCA] Add support for in-order CPUs
2021-03-04 14:08:19 +03:00
AArch64SchedA57.td
[AARCH64] Improve accumulator forwarding for Cortex-A57 model
2021-01-04 10:58:43 +00:00
AArch64SchedA57WriteRes.td
[AARCH64] Improve accumulator forwarding for Cortex-A57 model
2021-01-04 10:58:43 +00:00
AArch64SchedA64FX.td
[AArch64] Add Fujitsu A64FX scheduling model
2021-01-15 17:14:04 +09:00
AArch64SchedCyclone.td
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AArch64SchedExynosM3.td
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AArch64SchedExynosM4.td
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AArch64SchedExynosM5.td
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AArch64SchedFalkor.td
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AArch64SchedFalkorDetails.td
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AArch64SchedKryo.td
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AArch64SchedKryoDetails.td
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AArch64SchedPredExynos.td
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AArch64SchedPredicates.td
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AArch64SchedThunderX2T99.td
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AArch64SchedThunderX3T110.td
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AArch64SchedThunderX.td
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AArch64SchedTSV110.td
[AArch64] Add pipeline model for HiSilicon's TSV110
2020-11-07 01:23:00 +03:00
AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
2021-02-18 16:55:16 +00:00
AArch64SelectionDAGInfo.h
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
2021-02-18 16:55:16 +00:00
AArch64SIMDInstrOpt.cpp
[AArch64] reuse another map iterator. NFC
2020-09-28 11:30:21 -07:00
AArch64SLSHardening.cpp
[NFC] Clean up uses of MachineModuleInfoWrapperPass
2020-07-01 09:45:05 -07:00
AArch64SpeculationHardening.cpp
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AArch64StackTagging.cpp
[DebugInfo] Handle multiple variable location operands in IR
2021-03-09 16:44:38 +00:00
AArch64StackTaggingPreRA.cpp
[MTE] Pin the tagged base pointer to one of the stack slots.
2020-10-15 12:50:16 -07:00
AArch64StorePairSuppress.cpp
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AArch64Subtarget.cpp
AArch64: add apple-a14 as a CPU
2021-01-19 14:04:53 +00:00
AArch64Subtarget.h
[AArch64] Add Cortex CPU subtarget features for instruction fusion.
2021-01-25 09:11:29 +00:00
AArch64SVEInstrInfo.td
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
2021-02-18 16:55:16 +00:00
AArch64SystemOperands.td
[AArch64] Add +pauth archictecture option, allowing the v8.3a pointer authentication extension.
2021-01-08 13:21:11 +00:00
AArch64TargetMachine.cpp
[AArch64][GlobalISel] Enable use of the optsize predicate in the selector.
2021-03-02 12:55:51 -08:00
AArch64TargetMachine.h
Support addrspacecast initializers with isNoopAddrSpaceCast
2020-07-31 10:42:43 -04:00
AArch64TargetObjectFile.cpp
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AArch64TargetObjectFile.h
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AArch64TargetTransformInfo.cpp
[CostModel][SVE] Add cost model for shuffle reverse with i1 and scalable vector
2021-03-04 18:52:59 +00:00
AArch64TargetTransformInfo.h
[SVE] Add support for scalable vectorization of loops with int/fast FP reductions
2021-02-16 13:50:06 +00:00
CMakeLists.txt
[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP
2021-03-08 13:01:10 -08:00
SVEInstrFormats.td
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
2021-02-18 16:55:16 +00:00
SVEIntrinsicOpts.cpp
[AArch64][SVE] Coalesce ptrue instrinsic calls where possible
2021-02-05 10:43:28 +00:00