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llvm-project/llvm/test/CodeGen/MIR
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Stephen Tozer f677413071 Reapply "[DebugInfo] Add new instruction and DIExpression operator for variadic debug values" 
Rewrites test to use correct architecture triple; fixes incorrect
reference in SourceLevelDebugging doc; simplifies `spillReg` behaviour
so as to not be dependent on changes elsewhere in the patch stack.

This reverts commit d2000b45d033c06dc7973f59909a0ad12887ff51.
2021-03-05 12:32:05 +00:00
..
AArch64
[mir] Fix confusing MIR when MMO's value is nullptr but offset is non-zero
2021-03-04 10:34:30 -08:00
AMDGPU
Make fixed-abi default for AMD HSA OS
2021-02-19 15:05:25 +00:00
ARM
[ARM] Track epilogue instructions with FrameDestroy flag (NFC)
2020-03-18 13:32:59 +00:00
Generic
Revert "[DebugInfo] Add new instruction and DIExpression operator for variadic debug values"
2021-03-04 11:59:21 +00:00
Hexagon
Reland D73534: [DebugInfo] Enable the debug entry values feature by default
2020-03-19 13:57:30 +01:00
Mips
[MIParser] Set RegClassOrRegBank during instruction parsing
2019-10-22 14:25:37 +00:00
NVPTX
…
PowerPC
[PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC
2019-09-13 14:18:36 +00:00
WebAssembly
[WebAssembly] Fix tests missed in rL374235
2019-10-09 23:06:38 +00:00
X86
Reapply "[DebugInfo] Add new instruction and DIExpression operator for variadic debug values"
2021-03-05 12:32:05 +00:00
README
…

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.