llvm-project/clang/test/CodeGen/riscv-be-data-layout.c
Djordje Todorovic 84cdaa458a
Reland "[clang][RISCV] Add big-endian RISC-V target support" (#177939)
The problem was using the `--rtlib=platform` without
`--unwindlib=platform` conflicts the default unwindlib with the
Fuchsia's configuration, and that is why the test failed.

Orignal PR: https://github.com/llvm/llvm-project/pull/165599
The fail was reported at:
https://github.com/llvm/llvm-project/pull/165599#issuecomment-3751750804

Co-authored-by: Djordje Todorovic <djordje.todorovic@syrmia.com>
2026-02-05 10:53:54 +01:00

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C

// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64be-unknown-elf -emit-llvm %s -o - \
// RUN: | FileCheck %s --check-prefix=RV64
// RUN: %clang_cc1 -triple riscv32be-unknown-elf -emit-llvm %s -o - \
// RUN: | FileCheck %s --check-prefix=RV32
// RV64: target datalayout = "E-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
// RV32: target datalayout = "E-m:e-p:32:32-i64:64-n32-S128"
int foo(void) {
return 0;
}