b86503efe5
Classifying some memory instructions as VALU leads to unexpected behavior from the sched*barrier intrinsics.
60 lines
3.1 KiB
YAML
60 lines
3.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -run-pass=machine-scheduler -o - %s | FileCheck %s
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---
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name: buffer_load_lds_not_valu
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: buffer_load_lds_not_valu
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $exec = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF3]], [[V_ADD_U32_e32_]], implicit $exec
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; CHECK-NEXT: $m0 = S_MOV_B32 0
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; CHECK-NEXT: BUFFER_LOAD_DWORDX4_LDS_OFFEN [[DEF]], [[DEF1]], 0, 0, 0, 0, implicit $exec, implicit $m0
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; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_1]], implicit $exec
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; CHECK-NEXT: [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_ADD_U32_e32_1]], [[V_ADD_U32_e32_2]], implicit $exec
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; CHECK-NEXT: $m0 = S_MOV_B32 1
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; CHECK-NEXT: BUFFER_LOAD_DWORDX4_LDS_OFFEN [[DEF]], [[DEF1]], 0, 0, 0, 0, implicit $exec, implicit $m0
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; CHECK-NEXT: [[V_ADD_U32_e32_4:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_ADD_U32_e32_2]], [[V_ADD_U32_e32_3]], implicit $exec
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; CHECK-NEXT: [[V_ADD_U32_e32_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_ADD_U32_e32_3]], [[V_ADD_U32_e32_4]], implicit $exec
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; CHECK-NEXT: [[V_ADD_U32_e32_6:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_ADD_U32_e32_4]], [[V_ADD_U32_e32_5]], implicit $exec
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; CHECK-NEXT: dead [[V_ADD_U32_e32_7:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_ADD_U32_e32_5]], [[V_ADD_U32_e32_6]], implicit $exec
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 2, 0
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; CHECK-NEXT: SCHED_GROUP_BARRIER 4, 1, 0
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 2, 0
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; CHECK-NEXT: SCHED_GROUP_BARRIER 4, 1, 0
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 4, 0
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; CHECK-NEXT: S_ENDPGM 0
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$exec = IMPLICIT_DEF
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%0:vgpr_32 = IMPLICIT_DEF
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%1:sgpr_128 = IMPLICIT_DEF
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%2:vgpr_32 = IMPLICIT_DEF
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%3:vgpr_32 = IMPLICIT_DEF
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%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%5:vgpr_32 = V_ADD_U32_e32 %3, %4, implicit $exec
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$m0 = S_MOV_B32 0
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BUFFER_LOAD_DWORDX4_LDS_OFFEN %0, %1, 0, 0, 0, 0, implicit $exec, implicit $m0
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$m0 = S_MOV_B32 1
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BUFFER_LOAD_DWORDX4_LDS_OFFEN %0, %1, 0, 0, 0, 0, implicit $exec, implicit $m0
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%6:vgpr_32 = V_ADD_U32_e32 %4, %5, implicit $exec
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%7:vgpr_32 = V_ADD_U32_e32 %5, %6, implicit $exec
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%8:vgpr_32 = V_ADD_U32_e32 %6, %7, implicit $exec
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%9:vgpr_32 = V_ADD_U32_e32 %7, %8, implicit $exec
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%10:vgpr_32 = V_ADD_U32_e32 %8, %9, implicit $exec
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%11:vgpr_32 = V_ADD_U32_e32 %9, %10, implicit $exec
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SCHED_GROUP_BARRIER 2, 2, 0
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SCHED_GROUP_BARRIER 4, 1 ,0
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SCHED_GROUP_BARRIER 2, 2, 0
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SCHED_GROUP_BARRIER 4, 1 ,0
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SCHED_GROUP_BARRIER 2, 4, 0
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S_ENDPGM 0
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...
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