196548988e
This commit adds 4 Clang builtins for PowerPC AMO store operations: __builtin_amo_stwat for 32-bit unsigned operations __builtin_amo_stdat for 64-bit unsigned operations __builtin_amo_stwat_s for 32-bit signed operations __builtin_amo_stdat_s for 64-bit signed operations and maps GCC's AMO store functions to these Clang builtins for compatibility.
121 lines
3.6 KiB
LLVM
121 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names < %s \
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; RUN: | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix \
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; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names < %s \
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; RUN: | FileCheck %s --check-prefix=CHECK-BE
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define void @test_lwat(ptr noundef %ptr, i32 noundef %value, ptr nocapture %resp) {
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; CHECK-LABEL: test_lwat:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mr r7, r4
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; CHECK-NEXT: lwat r6, r3, 0
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; CHECK-NEXT: stw r6, 0(r5)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test_lwat:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: mr r7, r4
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; CHECK-BE-NEXT: lwat r6, r3, 0
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; CHECK-BE-NEXT: stw r6, 0(r5)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.amo.lwat(ptr %ptr, i32 %value, i32 0)
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store i32 %0, ptr %resp, align 4
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ret void
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}
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define void @test_ldat(ptr noundef %ptr, i64 noundef %value, ptr nocapture %resp) {
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; CHECK-LABEL: test_ldat:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mr r7, r4
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; CHECK-NEXT: ldat r6, r3, 0
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; CHECK-NEXT: std r6, 0(r5)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test_ldat:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: mr r7, r4
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; CHECK-BE-NEXT: ldat r6, r3, 0
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; CHECK-BE-NEXT: std r6, 0(r5)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = tail call i64 @llvm.ppc.amo.ldat(ptr %ptr, i64 %value, i32 0)
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store i64 %0, ptr %resp, align 8
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ret void
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}
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define void @test_lwat_cond(ptr noundef %ptr, ptr nocapture %resp) {
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; CHECK-LABEL: test_lwat_cond:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lwat r6, r3, 24
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; CHECK-NEXT: stw r6, 0(r4)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test_lwat_cond:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lwat r6, r3, 24
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; CHECK-BE-NEXT: stw r6, 0(r4)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.amo.lwat.cond(ptr %ptr, i32 24)
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store i32 %0, ptr %resp, align 4
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ret void
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}
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define void @test_ldat_cond(ptr noundef %ptr, ptr nocapture %resp) {
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; CHECK-LABEL: test_ldat_cond:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ldat r6, r3, 24
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; CHECK-NEXT: std r6, 0(r4)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test_ldat_cond:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: ldat r6, r3, 24
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; CHECK-BE-NEXT: std r6, 0(r4)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = tail call i64 @llvm.ppc.amo.ldat.cond(ptr %ptr, i32 24)
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store i64 %0, ptr %resp, align 8
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ret void
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}
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define void @test_stwat(ptr noundef %ptr, i32 noundef %value) {
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; CHECK-LABEL: test_stwat:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stwat r4, r3, 0
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test_stwat:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: stwat r4, r3, 0
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; CHECK-BE-NEXT: blr
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entry:
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tail call void @llvm.ppc.amo.stwat(ptr %ptr, i32 %value, i32 0)
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ret void
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}
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define void @test_stdat(ptr noundef %ptr, i64 noundef %value) {
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; CHECK-LABEL: test_stdat:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stdat r4, r3, 0
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test_stdat:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: stdat r4, r3, 0
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; CHECK-BE-NEXT: blr
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entry:
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tail call void @llvm.ppc.amo.stdat(ptr %ptr, i64 %value, i32 0)
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ret void
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}
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declare i64 @llvm.ppc.amo.ldat(ptr, i64, i32 immarg)
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declare i32 @llvm.ppc.amo.lwat(ptr, i32, i32 immarg)
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declare i64 @llvm.ppc.amo.ldat.cond(ptr, i32 immarg)
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declare i32 @llvm.ppc.amo.lwat.cond(ptr, i32 immarg)
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declare void @llvm.ppc.amo.stwat(ptr, i32, i32 immarg)
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declare void @llvm.ppc.amo.stdat(ptr, i64, i32 immarg)
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