db26ce5c55
On PowerPC targets, `half` uses the default legalization of promoting to a `f32`. However, this has some fundamental issues related to inability to round trip. Resolve this by switching to the soft legalization, which passes `f16` as an `i16`. The PowerPC ABI Specification does not define a `_Float16` type, so the calling convention changes are acceptable. Fixes the PowerPC part of https://github.com/llvm/llvm-project/issues/97975 Fixes the PowerPC part of https://github.com/llvm/llvm-project/issues/97981
28 lines
918 B
LLVM
28 lines
918 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
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; RUN: -check-prefix=CHECK-P9
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define dso_local half @test2(i64 %a, i64 %b) local_unnamed_addr #0 {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: add r3, r4, r3
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; CHECK-NEXT: addi r3, r3, 11
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: test2:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: add r3, r4, r3
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; CHECK-P9-NEXT: addi r3, r3, 11
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; CHECK-P9-NEXT: blr
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entry:
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%add = add i64 %b, %a
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%0 = trunc i64 %add to i16
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%conv = add i16 %0, 11
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%call = bitcast i16 %conv to half
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ret half %call
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}
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attributes #0 = { nounwind }
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