SiliconA-Z b4797d4c03
[PowerPC] Fix miscompilation when using 32-bit ucmp on 64-bit PowerPC (#178979)
I forgot that you need to clear the upper 32 bits for the carry flag to
work properly on ppc64 or else there will be garbage and possibly
incorrect results.

Fixes: https://github.com/llvm/llvm-project/issues/179119

I do not have merge permissions.
2026-02-02 09:00:40 +01:00

115 lines
3.0 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=ppc64le-unknown-unknown %s -o - | FileCheck %s
define i8 @ucmp_8_8(i8 zeroext %x, i8 zeroext %y) nounwind {
; CHECK-LABEL: ucmp_8_8:
; CHECK: # %bb.0:
; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: clrldi 4, 4, 32
; CHECK-NEXT: sub 5, 3, 4
; CHECK-NEXT: subc 6, 4, 3
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
%1 = call i8 @llvm.ucmp(i8 %x, i8 %y)
ret i8 %1
}
define i8 @ucmp_8_16(i16 zeroext %x, i16 zeroext %y) nounwind {
; CHECK-LABEL: ucmp_8_16:
; CHECK: # %bb.0:
; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: clrldi 4, 4, 32
; CHECK-NEXT: sub 5, 3, 4
; CHECK-NEXT: subc 6, 4, 3
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
%1 = call i8 @llvm.ucmp(i16 %x, i16 %y)
ret i8 %1
}
define i8 @ucmp_8_32(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: ucmp_8_32:
; CHECK: # %bb.0:
; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: clrldi 4, 4, 32
; CHECK-NEXT: sub 5, 3, 4
; CHECK-NEXT: subc 6, 4, 3
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
%1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
ret i8 %1
}
define i8 @ucmp_8_64(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: ucmp_8_64:
; CHECK: # %bb.0:
; CHECK-NEXT: subc 6, 4, 3
; CHECK-NEXT: sub 5, 3, 4
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
%1 = call i8 @llvm.ucmp(i64 %x, i64 %y)
ret i8 %1
}
define i8 @ucmp_8_128(i128 %x, i128 %y) nounwind {
; CHECK-LABEL: ucmp_8_128:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpld 4, 6
; CHECK-NEXT: cmpld 1, 3, 5
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: li 4, -1
; CHECK-NEXT: crandc 20, 1, 2
; CHECK-NEXT: crand 21, 2, 5
; CHECK-NEXT: crnor 20, 21, 20
; CHECK-NEXT: crand 21, 2, 4
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: crandc 20, 0, 2
; CHECK-NEXT: cror 20, 21, 20
; CHECK-NEXT: isel 3, 4, 3, 20
; CHECK-NEXT: blr
%1 = call i8 @llvm.ucmp(i128 %x, i128 %y)
ret i8 %1
}
define i32 @ucmp_32_32(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: ucmp_32_32:
; CHECK: # %bb.0:
; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: clrldi 4, 4, 32
; CHECK-NEXT: sub 5, 3, 4
; CHECK-NEXT: subc 6, 4, 3
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
ret i32 %1
}
define i32 @ucmp_32_64(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: ucmp_32_64:
; CHECK: # %bb.0:
; CHECK-NEXT: subc 6, 4, 3
; CHECK-NEXT: sub 5, 3, 4
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
%1 = call i32 @llvm.ucmp(i64 %x, i64 %y)
ret i32 %1
}
define i64 @ucmp_64_64(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: ucmp_64_64:
; CHECK: # %bb.0:
; CHECK-NEXT: subc 6, 4, 3
; CHECK-NEXT: sub 5, 3, 4
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
%1 = call i64 @llvm.ucmp(i64 %x, i64 %y)
ret i64 %1
}