7ea33e6848
The first input operand of SUBREG_TO_REG was an immediate that most targets set to 0. In practice it had no effect on codegen. Remove it.
36 lines
2.1 KiB
LLVM
36 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-ibm-aix -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -stop-after=finalize-isel -verify-machineinstrs < %s | \
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; RUN: FileCheck %s
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define <4 x i1> @foo(i1 %c1, i1 %c2, i1 %c3) {
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; CHECK-LABEL: name: foo
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; CHECK: bb.0 (%ir-block.0):
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; CHECK-NEXT: liveins: $x3, $x4, $x5
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x5
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc = COPY $x4
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:g8rc = COPY $x3
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprc = COPY [[COPY1]].sub_32
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; CHECK-NEXT: [[MTVSRWZ:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY3]]
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:vrrc = SUBREG_TO_REG killed [[MTVSRWZ]], %subreg.sub_64
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprc = COPY [[COPY2]].sub_32
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; CHECK-NEXT: [[MTVSRWZ1:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY4]]
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; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:vrrc = SUBREG_TO_REG killed [[MTVSRWZ1]], %subreg.sub_64
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; CHECK-NEXT: [[VMRGOW:%[0-9]+]]:vrrc = VMRGOW killed [[SUBREG_TO_REG1]], killed [[SUBREG_TO_REG]]
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; CHECK-NEXT: [[LDtocCPT:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtocCPT %const.0, $x2 :: (load (s64) from got)
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; CHECK-NEXT: [[LXV:%[0-9]+]]:vsrc = LXV 0, killed [[LDtocCPT]] :: (load (s128) from constant-pool)
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
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; CHECK-NEXT: [[MTVSRWZ2:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY5]]
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; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:vsrc = SUBREG_TO_REG killed [[MTVSRWZ2]], %subreg.sub_64
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; CHECK-NEXT: [[XXPERM:%[0-9]+]]:vsrc = XXPERM killed [[VMRGOW]], [[SUBREG_TO_REG2]], killed [[LXV]]
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; CHECK-NEXT: [[XXINSERTW:%[0-9]+]]:vsrc = XXINSERTW [[XXPERM]], [[XXPERM]], 8
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; CHECK-NEXT: $v2 = COPY [[XXINSERTW]]
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; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $v2
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%1 = insertelement <4 x i1> poison, i1 %c1, i64 0
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%2 = insertelement <4 x i1> %1, i1 %c2, i64 1
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%3 = insertelement <4 x i1> %2, i1 %c3, i64 3
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%4 = shufflevector <4 x i1> %3, <4 x i1> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 3>
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ret <4 x i1> %4
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}
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