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llvm-project/llvm/test/CodeGen/SystemZ/vec-abi-01.ll
Jonas Paulsson c999e9a4fe
[SystemZ] Support fp16 vector ABI and basic codegen. (#171066) 
- Make v8f16 a legal type so that arguments can be passed in vector
registers. Handle fp16 vectors so that they have the same ABI as other
fp vectors.

- Set the preferred vector action for fp16 vectors to "split". This will
scalarize all operations, which is not always necessary (like with
memory operations), but it avoids the superfluous operations that result
after first widening and then scalarizing a narrow vector (like v4f16).

Fixes #168992
2026-01-26 13:42:25 -06:00

2490 lines
88 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
;
; Test passing vector arguments per the ABI for z10 (without vector support).
; The function names codify the element type and the size of the vector in
; bytes, just like in the clang test systemz-abi-vector.c
@global_char_1 = global <1 x i8> zeroinitializer, align 2
@global_char_8 = global <8 x i8> zeroinitializer, align 8
@global_char_16 = global <16 x i8> zeroinitializer, align 16
@global_char_32 = global <32 x i8> zeroinitializer, align 32
@global_short_2 = global <1 x i16> zeroinitializer, align 2
@global_short_8 = global <4 x i16> zeroinitializer, align 8
@global_short_16 = global <8 x i16> zeroinitializer, align 16
@global_int_4 = global <1 x i32> zeroinitializer, align 4
@global_int_8 = global <2 x i32> zeroinitializer, align 8
@global_int_16 = global <4 x i32> zeroinitializer, align 16
@global_int_32 = global <8 x i32> zeroinitializer, align 32
@global_long_8 = global <1 x i64> zeroinitializer, align 8
@global_long_16 = global <2 x i64> zeroinitializer, align 16
@global___int128_16 = global <1 x i128> zeroinitializer, align 16
@global___int128_32 = global <2 x i128> zeroinitializer, align 32
@global__Float16_2 = global <1 x half> zeroinitializer, align 2
@global__Float16_8 = global <4 x half> zeroinitializer, align 8
@global__Float16_16 = global <8 x half> zeroinitializer, align 16
@global__Float16_32 = global <16 x half> zeroinitializer, align 32
@global_float_4 = global <1 x float> zeroinitializer, align 4
@global_float_8 = global <2 x float> zeroinitializer, align 8
@global_float_16 = global <4 x float> zeroinitializer, align 16
@global_double_8 = global <1 x double> zeroinitializer, align 8
@global_double_16 = global <2 x double> zeroinitializer, align 16
@global_double_32 = global <4 x double> zeroinitializer, align 32
@global_long_double_16 = global <1 x fp128> zeroinitializer, align 16
@global_long_double_32 = global <2 x fp128> zeroinitializer, align 32
define void @takeAndStore_char_1(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_char_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lb %r0, 0(%r2)
; CHECK-NEXT: lgrl %r1, global_char_1@GOT
; CHECK-NEXT: stc %r0, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <1 x i8>, ptr %0, align 1
store <1 x i8> %x, ptr @global_char_1, align 2
ret void
}
define void @takeAndStore_char_8(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_char_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: lh %r0, 0(%r2)
; CHECK-NEXT: lb %r1, 2(%r2)
; CHECK-NEXT: lb %r3, 3(%r2)
; CHECK-NEXT: lb %r4, 7(%r2)
; CHECK-NEXT: lgrl %r5, global_char_8@GOT
; CHECK-NEXT: lb %r14, 6(%r2)
; CHECK-NEXT: lb %r13, 5(%r2)
; CHECK-NEXT: lb %r2, 4(%r2)
; CHECK-NEXT: stc %r4, 7(%r5)
; CHECK-NEXT: stc %r14, 6(%r5)
; CHECK-NEXT: stc %r13, 5(%r5)
; CHECK-NEXT: stc %r2, 4(%r5)
; CHECK-NEXT: stc %r3, 3(%r5)
; CHECK-NEXT: stc %r1, 2(%r5)
; CHECK-NEXT: sth %r0, 0(%r5)
; CHECK-NEXT: lmg %r13, %r15, 104(%r15)
; CHECK-NEXT: br %r14
entry:
%x = load <8 x i8>, ptr %0, align 8
store <8 x i8> %x, ptr @global_char_8, align 8
ret void
}
define void @takeAndStore_char_16(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_char_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lg %r0, 8(%r2)
; CHECK-NEXT: lgrl %r1, global_char_16@GOT
; CHECK-NEXT: lg %r2, 0(%r2)
; CHECK-NEXT: stg %r0, 8(%r1)
; CHECK-NEXT: stg %r2, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <16 x i8>, ptr %0, align 16
store <16 x i8> %x, ptr @global_char_16, align 16
ret void
}
define void @takeAndStore_char_32(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_char_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lg %r0, 24(%r2)
; CHECK-NEXT: lgrl %r1, global_char_32@GOT
; CHECK-NEXT: lg %r3, 16(%r2)
; CHECK-NEXT: lg %r4, 8(%r2)
; CHECK-NEXT: lg %r2, 0(%r2)
; CHECK-NEXT: stg %r0, 24(%r1)
; CHECK-NEXT: stg %r3, 16(%r1)
; CHECK-NEXT: stg %r4, 8(%r1)
; CHECK-NEXT: stg %r2, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <32 x i8>, ptr %0, align 32
store <32 x i8> %x, ptr @global_char_32, align 32
ret void
}
define void @takeAndStore_short_2(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_short_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lh %r0, 0(%r2)
; CHECK-NEXT: lgrl %r1, global_short_2@GOT
; CHECK-NEXT: sth %r0, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <1 x i16>, ptr %0, align 2
store <1 x i16> %x, ptr @global_short_2, align 2
ret void
}
define void @takeAndStore_short_8(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_short_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lh %r0, 6(%r2)
; CHECK-NEXT: lgrl %r1, global_short_8@GOT
; CHECK-NEXT: lh %r3, 4(%r2)
; CHECK-NEXT: l %r2, 0(%r2)
; CHECK-NEXT: sth %r0, 6(%r1)
; CHECK-NEXT: sth %r3, 4(%r1)
; CHECK-NEXT: st %r2, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <4 x i16>, ptr %0, align 8
store <4 x i16> %x, ptr @global_short_8, align 8
ret void
}
define void @takeAndStore_short_16(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_short_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: l %r0, 0(%r2)
; CHECK-NEXT: lh %r1, 4(%r2)
; CHECK-NEXT: lh %r3, 6(%r2)
; CHECK-NEXT: lh %r4, 14(%r2)
; CHECK-NEXT: lgrl %r5, global_short_16@GOT
; CHECK-NEXT: lh %r14, 12(%r2)
; CHECK-NEXT: lh %r13, 10(%r2)
; CHECK-NEXT: lh %r2, 8(%r2)
; CHECK-NEXT: sth %r4, 14(%r5)
; CHECK-NEXT: sth %r14, 12(%r5)
; CHECK-NEXT: sth %r13, 10(%r5)
; CHECK-NEXT: sth %r2, 8(%r5)
; CHECK-NEXT: sth %r3, 6(%r5)
; CHECK-NEXT: sth %r1, 4(%r5)
; CHECK-NEXT: st %r0, 0(%r5)
; CHECK-NEXT: lmg %r13, %r15, 104(%r15)
; CHECK-NEXT: br %r14
entry:
%x = load <8 x i16>, ptr %0, align 16
store <8 x i16> %x, ptr @global_short_16, align 16
ret void
}
define void @takeAndStore_int_4(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_int_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: l %r0, 0(%r2)
; CHECK-NEXT: lgrl %r1, global_int_4@GOT
; CHECK-NEXT: st %r0, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <1 x i32>, ptr %0, align 4
store <1 x i32> %x, ptr @global_int_4, align 4
ret void
}
define void @takeAndStore_int_8(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_int_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lg %r0, 0(%r2)
; CHECK-NEXT: lgrl %r1, global_int_8@GOT
; CHECK-NEXT: stg %r0, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <2 x i32>, ptr %0, align 8
store <2 x i32> %x, ptr @global_int_8, align 8
ret void
}
define void @takeAndStore_int_16(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_int_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: l %r0, 12(%r2)
; CHECK-NEXT: lgrl %r1, global_int_16@GOT
; CHECK-NEXT: l %r3, 8(%r2)
; CHECK-NEXT: lg %r2, 0(%r2)
; CHECK-NEXT: st %r0, 12(%r1)
; CHECK-NEXT: st %r3, 8(%r1)
; CHECK-NEXT: stg %r2, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <4 x i32>, ptr %0, align 16
store <4 x i32> %x, ptr @global_int_16, align 16
ret void
}
define void @takeAndStore_int_32(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_int_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: l %r0, 8(%r2)
; CHECK-NEXT: l %r1, 12(%r2)
; CHECK-NEXT: l %r3, 16(%r2)
; CHECK-NEXT: l %r4, 28(%r2)
; CHECK-NEXT: lgrl %r5, global_int_32@GOT
; CHECK-NEXT: l %r14, 24(%r2)
; CHECK-NEXT: l %r13, 20(%r2)
; CHECK-NEXT: lg %r2, 0(%r2)
; CHECK-NEXT: st %r4, 28(%r5)
; CHECK-NEXT: st %r14, 24(%r5)
; CHECK-NEXT: st %r13, 20(%r5)
; CHECK-NEXT: st %r3, 16(%r5)
; CHECK-NEXT: st %r1, 12(%r5)
; CHECK-NEXT: st %r0, 8(%r5)
; CHECK-NEXT: stg %r2, 0(%r5)
; CHECK-NEXT: lmg %r13, %r15, 104(%r15)
; CHECK-NEXT: br %r14
entry:
%x = load <8 x i32>, ptr %0, align 32
store <8 x i32> %x, ptr @global_int_32, align 32
ret void
}
define void @takeAndStore_long_8(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_long_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lg %r0, 0(%r2)
; CHECK-NEXT: lgrl %r1, global_long_8@GOT
; CHECK-NEXT: stg %r0, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <1 x i64>, ptr %0, align 8
store <1 x i64> %x, ptr @global_long_8, align 8
ret void
}
define void @takeAndStore_long_16(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_long_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lg %r0, 8(%r2)
; CHECK-NEXT: lgrl %r1, global_long_16@GOT
; CHECK-NEXT: lg %r2, 0(%r2)
; CHECK-NEXT: stg %r0, 8(%r1)
; CHECK-NEXT: stg %r2, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <2 x i64>, ptr %0, align 16
store <2 x i64> %x, ptr @global_long_16, align 16
ret void
}
define void @takeAndStore___int128_16(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore___int128_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lg %r0, 0(%r2)
; CHECK-NEXT: lgrl %r1, global___int128_16@GOT
; CHECK-NEXT: lg %r2, 8(%r2)
; CHECK-NEXT: stg %r0, 0(%r1)
; CHECK-NEXT: stg %r2, 8(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <1 x i128>, ptr %0, align 16
store <1 x i128> %x, ptr @global___int128_16, align 16
ret void
}
define void @takeAndStore___int128_32(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore___int128_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lg %r0, 16(%r2)
; CHECK-NEXT: lgrl %r1, global___int128_32@GOT
; CHECK-NEXT: lg %r3, 24(%r2)
; CHECK-NEXT: lg %r4, 0(%r2)
; CHECK-NEXT: lg %r2, 8(%r2)
; CHECK-NEXT: stg %r0, 16(%r1)
; CHECK-NEXT: stg %r3, 24(%r1)
; CHECK-NEXT: stg %r4, 0(%r1)
; CHECK-NEXT: stg %r2, 8(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <2 x i128>, ptr %0, align 32
store <2 x i128> %x, ptr @global___int128_32, align 32
ret void
}
define void @takeAndStore__Float16_2(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore__Float16_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgh %r0, 0(%r2)
; CHECK-NEXT: sllg %r0, %r0, 48
; CHECK-NEXT: lgrl %r1, global__Float16_2@GOT
; CHECK-NEXT: ldgr %f0, %r0
; CHECK-NEXT: lgdr %r0, %f0
; CHECK-NEXT: srlg %r0, %r0, 48
; CHECK-NEXT: sth %r0, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <1 x half>, ptr %0, align 2
store <1 x half> %x, ptr @global__Float16_2, align 2
ret void
}
define void @takeAndStore__Float16_8(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore__Float16_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgh %r0, 4(%r2)
; CHECK-NEXT: sllg %r0, %r0, 48
; CHECK-NEXT: lgh %r1, 6(%r2)
; CHECK-NEXT: l %r2, 0(%r2)
; CHECK-NEXT: lgrl %r3, global__Float16_8@GOT
; CHECK-NEXT: ldgr %f0, %r0
; CHECK-NEXT: sllg %r0, %r1, 48
; CHECK-NEXT: ldgr %f1, %r0
; CHECK-NEXT: st %r2, 0(%r3)
; CHECK-NEXT: lgdr %r0, %f1
; CHECK-NEXT: srlg %r0, %r0, 48
; CHECK-NEXT: sth %r0, 6(%r3)
; CHECK-NEXT: lgdr %r0, %f0
; CHECK-NEXT: srlg %r0, %r0, 48
; CHECK-NEXT: sth %r0, 4(%r3)
; CHECK-NEXT: br %r14
entry:
%x = load <4 x half>, ptr %0, align 8
store <4 x half> %x, ptr @global__Float16_8, align 8
ret void
}
define void @takeAndStore__Float16_16(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore__Float16_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgh %r0, 4(%r2)
; CHECK-NEXT: lgh %r1, 6(%r2)
; CHECK-NEXT: sllg %r0, %r0, 48
; CHECK-NEXT: ldgr %f0, %r0
; CHECK-NEXT: lgh %r0, 8(%r2)
; CHECK-NEXT: sllg %r1, %r1, 48
; CHECK-NEXT: ldgr %f1, %r1
; CHECK-NEXT: lgh %r1, 10(%r2)
; CHECK-NEXT: sllg %r0, %r0, 48
; CHECK-NEXT: lgh %r3, 12(%r2)
; CHECK-NEXT: ldgr %f2, %r0
; CHECK-NEXT: sllg %r0, %r1, 48
; CHECK-NEXT: ldgr %f3, %r0
; CHECK-NEXT: sllg %r0, %r3, 48
; CHECK-NEXT: lgh %r3, 14(%r2)
; CHECK-NEXT: l %r2, 0(%r2)
; CHECK-NEXT: lgrl %r1, global__Float16_16@GOT
; CHECK-NEXT: ldgr %f4, %r0
; CHECK-NEXT: sllg %r0, %r3, 48
; CHECK-NEXT: ldgr %f5, %r0
; CHECK-NEXT: st %r2, 0(%r1)
; CHECK-NEXT: lgdr %r0, %f5
; CHECK-NEXT: srlg %r0, %r0, 48
; CHECK-NEXT: sth %r0, 14(%r1)
; CHECK-NEXT: lgdr %r0, %f4
; CHECK-NEXT: srlg %r0, %r0, 48
; CHECK-NEXT: sth %r0, 12(%r1)
; CHECK-NEXT: lgdr %r0, %f3
; CHECK-NEXT: srlg %r0, %r0, 48
; CHECK-NEXT: sth %r0, 10(%r1)
; CHECK-NEXT: lgdr %r0, %f2
; CHECK-NEXT: srlg %r0, %r0, 48
; CHECK-NEXT: sth %r0, 8(%r1)
; CHECK-NEXT: lgdr %r0, %f1
; CHECK-NEXT: srlg %r0, %r0, 48
; CHECK-NEXT: sth %r0, 6(%r1)
; CHECK-NEXT: lgdr %r0, %f0
; CHECK-NEXT: srlg %r0, %r0, 48
; CHECK-NEXT: sth %r0, 4(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <8 x half>, ptr %0, align 16
store <8 x half> %x, ptr @global__Float16_16, align 16
ret void
}
define void @takeAndStore__Float16_32(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore__Float16_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lg %r0, 24(%r2)
; CHECK-NEXT: lgrl %r1, global__Float16_32@GOT
; CHECK-NEXT: lg %r3, 16(%r2)
; CHECK-NEXT: lg %r4, 8(%r2)
; CHECK-NEXT: lg %r2, 0(%r2)
; CHECK-NEXT: stg %r0, 24(%r1)
; CHECK-NEXT: stg %r3, 16(%r1)
; CHECK-NEXT: stg %r4, 8(%r1)
; CHECK-NEXT: stg %r2, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <16 x half>, ptr %0, align 32
store <16 x half> %x, ptr @global__Float16_32, align 32
ret void
}
define void @takeAndStore_float_4(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_float_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: le %f0, 0(%r2)
; CHECK-NEXT: lgrl %r1, global_float_4@GOT
; CHECK-NEXT: ste %f0, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <1 x float>, ptr %0, align 4
store <1 x float> %x, ptr @global_float_4, align 4
ret void
}
define void @takeAndStore_float_8(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_float_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lg %r0, 0(%r2)
; CHECK-NEXT: lgrl %r1, global_float_8@GOT
; CHECK-NEXT: stg %r0, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <2 x float>, ptr %0, align 8
store <2 x float> %x, ptr @global_float_8, align 8
ret void
}
define void @takeAndStore_float_16(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_float_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: le %f0, 12(%r2)
; CHECK-NEXT: lgrl %r1, global_float_16@GOT
; CHECK-NEXT: le %f1, 8(%r2)
; CHECK-NEXT: lg %r0, 0(%r2)
; CHECK-NEXT: ste %f0, 12(%r1)
; CHECK-NEXT: ste %f1, 8(%r1)
; CHECK-NEXT: stg %r0, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <4 x float>, ptr %0, align 16
store <4 x float> %x, ptr @global_float_16, align 16
ret void
}
define void @takeAndStore_double_8(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_double_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld %f0, 0(%r2)
; CHECK-NEXT: lgrl %r1, global_double_8@GOT
; CHECK-NEXT: std %f0, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <1 x double>, ptr %0, align 8
store <1 x double> %x, ptr @global_double_8, align 8
ret void
}
define void @takeAndStore_double_16(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld %f0, 8(%r2)
; CHECK-NEXT: lgrl %r1, global_double_16@GOT
; CHECK-NEXT: ld %f1, 0(%r2)
; CHECK-NEXT: std %f0, 8(%r1)
; CHECK-NEXT: std %f1, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <2 x double>, ptr %0, align 16
store <2 x double> %x, ptr @global_double_16, align 16
ret void
}
define void @takeAndStore_double_32(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld %f0, 24(%r2)
; CHECK-NEXT: lgrl %r1, global_double_32@GOT
; CHECK-NEXT: ld %f1, 16(%r2)
; CHECK-NEXT: ld %f2, 8(%r2)
; CHECK-NEXT: ld %f3, 0(%r2)
; CHECK-NEXT: std %f0, 24(%r1)
; CHECK-NEXT: std %f1, 16(%r1)
; CHECK-NEXT: std %f2, 8(%r1)
; CHECK-NEXT: std %f3, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <4 x double>, ptr %0, align 32
store <4 x double> %x, ptr @global_double_32, align 32
ret void
}
define void @takeAndStore_long_double_16(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_long_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld %f0, 0(%r2)
; CHECK-NEXT: ld %f2, 8(%r2)
; CHECK-NEXT: lgrl %r1, global_long_double_16@GOT
; CHECK-NEXT: std %f0, 0(%r1)
; CHECK-NEXT: std %f2, 8(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <1 x fp128>, ptr %0, align 16
store <1 x fp128> %x, ptr @global_long_double_16, align 16
ret void
}
define void @takeAndStore_long_double_32(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_long_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld %f0, 16(%r2)
; CHECK-NEXT: ld %f2, 24(%r2)
; CHECK-NEXT: lgrl %r1, global_long_double_32@GOT
; CHECK-NEXT: ld %f1, 0(%r2)
; CHECK-NEXT: ld %f3, 8(%r2)
; CHECK-NEXT: std %f0, 16(%r1)
; CHECK-NEXT: std %f2, 24(%r1)
; CHECK-NEXT: std %f1, 0(%r1)
; CHECK-NEXT: std %f3, 8(%r1)
; CHECK-NEXT: br %r14
entry:
%x = load <2 x fp128>, ptr %0, align 32
store <2 x fp128> %x, ptr @global_long_double_32, align 32
ret void
}
define void @loadAndReturn_char_1(ptr dead_on_unwind noalias writable writeonly sret(<1 x i8>) align 1 captures(none) initializes((0, 1)) %agg.result) {
; CHECK-LABEL: loadAndReturn_char_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_char_1@GOT
; CHECK-NEXT: mvc 0(1,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x i8>, ptr @global_char_1, align 2
store <1 x i8> %0, ptr %agg.result, align 1
ret void
}
define void @loadAndReturn_char_8(ptr dead_on_unwind noalias writable writeonly sret(<8 x i8>) align 8 captures(none) initializes((0, 8)) %agg.result) {
; CHECK-LABEL: loadAndReturn_char_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_char_8@GOT
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <8 x i8>, ptr @global_char_8, align 8
store <8 x i8> %0, ptr %agg.result, align 8
ret void
}
define void @loadAndReturn_char_16(ptr dead_on_unwind noalias writable writeonly sret(<16 x i8>) align 16 captures(none) initializes((0, 16)) %agg.result) {
; CHECK-LABEL: loadAndReturn_char_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_char_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <16 x i8>, ptr @global_char_16, align 16
store <16 x i8> %0, ptr %agg.result, align 16
ret void
}
define void @loadAndReturn_char_32(ptr dead_on_unwind noalias writable writeonly sret(<32 x i8>) align 32 captures(none) initializes((0, 32)) %agg.result) {
; CHECK-LABEL: loadAndReturn_char_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_char_32@GOT
; CHECK-NEXT: mvc 24(8,%r2), 24(%r1)
; CHECK-NEXT: mvc 16(8,%r2), 16(%r1)
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <32 x i8>, ptr @global_char_32, align 32
store <32 x i8> %0, ptr %agg.result, align 32
ret void
}
define void @loadAndReturn_short_2(ptr dead_on_unwind noalias writable writeonly sret(<1 x i16>) align 2 captures(none) initializes((0, 2)) %agg.result) {
; CHECK-LABEL: loadAndReturn_short_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_short_2@GOT
; CHECK-NEXT: mvc 0(2,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x i16>, ptr @global_short_2, align 2
store <1 x i16> %0, ptr %agg.result, align 2
ret void
}
define void @loadAndReturn_short_8(ptr dead_on_unwind noalias writable writeonly sret(<4 x i16>) align 8 captures(none) initializes((0, 8)) %agg.result) {
; CHECK-LABEL: loadAndReturn_short_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_short_8@GOT
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <4 x i16>, ptr @global_short_8, align 8
store <4 x i16> %0, ptr %agg.result, align 8
ret void
}
define void @loadAndReturn_short_16(ptr dead_on_unwind noalias writable writeonly sret(<8 x i16>) align 16 captures(none) initializes((0, 16)) %agg.result) {
; CHECK-LABEL: loadAndReturn_short_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_short_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <8 x i16>, ptr @global_short_16, align 16
store <8 x i16> %0, ptr %agg.result, align 16
ret void
}
define void @loadAndReturn_int_4(ptr dead_on_unwind noalias writable writeonly sret(<1 x i32>) align 4 captures(none) initializes((0, 4)) %agg.result) {
; CHECK-LABEL: loadAndReturn_int_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_int_4@GOT
; CHECK-NEXT: mvc 0(4,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x i32>, ptr @global_int_4, align 4
store <1 x i32> %0, ptr %agg.result, align 4
ret void
}
define void @loadAndReturn_int_8(ptr dead_on_unwind noalias writable writeonly sret(<2 x i32>) align 8 captures(none) initializes((0, 8)) %agg.result) {
; CHECK-LABEL: loadAndReturn_int_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_int_8@GOT
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <2 x i32>, ptr @global_int_8, align 8
store <2 x i32> %0, ptr %agg.result, align 8
ret void
}
define void @loadAndReturn_int_16(ptr dead_on_unwind noalias writable writeonly sret(<4 x i32>) align 16 captures(none) initializes((0, 16)) %agg.result) {
; CHECK-LABEL: loadAndReturn_int_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_int_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <4 x i32>, ptr @global_int_16, align 16
store <4 x i32> %0, ptr %agg.result, align 16
ret void
}
define void @loadAndReturn_int_32(ptr dead_on_unwind noalias writable writeonly sret(<8 x i32>) align 32 captures(none) initializes((0, 32)) %agg.result) {
; CHECK-LABEL: loadAndReturn_int_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_int_32@GOT
; CHECK-NEXT: mvc 24(8,%r2), 24(%r1)
; CHECK-NEXT: mvc 16(8,%r2), 16(%r1)
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <8 x i32>, ptr @global_int_32, align 32
store <8 x i32> %0, ptr %agg.result, align 32
ret void
}
define void @loadAndReturn_long_8(ptr dead_on_unwind noalias writable writeonly sret(<1 x i64>) align 8 captures(none) initializes((0, 8)) %agg.result) {
; CHECK-LABEL: loadAndReturn_long_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_long_8@GOT
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x i64>, ptr @global_long_8, align 8
store <1 x i64> %0, ptr %agg.result, align 8
ret void
}
define void @loadAndReturn_long_16(ptr dead_on_unwind noalias writable writeonly sret(<2 x i64>) align 16 captures(none) initializes((0, 16)) %agg.result) {
; CHECK-LABEL: loadAndReturn_long_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_long_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <2 x i64>, ptr @global_long_16, align 16
store <2 x i64> %0, ptr %agg.result, align 16
ret void
}
define void @loadAndReturn___int128_16(ptr dead_on_unwind noalias writable writeonly sret(<1 x i128>) align 16 captures(none) initializes((0, 16)) %agg.result) {
; CHECK-LABEL: loadAndReturn___int128_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global___int128_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x i128>, ptr @global___int128_16, align 16
store <1 x i128> %0, ptr %agg.result, align 16
ret void
}
define void @loadAndReturn___int128_32(ptr dead_on_unwind noalias writable writeonly sret(<2 x i128>) align 32 captures(none) initializes((0, 32)) %agg.result) {
; CHECK-LABEL: loadAndReturn___int128_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global___int128_32@GOT
; CHECK-NEXT: mvc 24(8,%r2), 24(%r1)
; CHECK-NEXT: mvc 16(8,%r2), 16(%r1)
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <2 x i128>, ptr @global___int128_32, align 32
store <2 x i128> %0, ptr %agg.result, align 32
ret void
}
define void @loadAndReturn__Float16_2(ptr dead_on_unwind noalias writable writeonly sret(<1 x half>) align 2 captures(none) initializes((0, 2)) %agg.result) {
; CHECK-LABEL: loadAndReturn__Float16_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global__Float16_2@GOT
; CHECK-NEXT: lgh %r0, 0(%r1)
; CHECK-NEXT: sllg %r0, %r0, 48
; CHECK-NEXT: ldgr %f0, %r0
; CHECK-NEXT: lgdr %r0, %f0
; CHECK-NEXT: srlg %r0, %r0, 48
; CHECK-NEXT: sth %r0, 0(%r2)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x half>, ptr @global__Float16_2, align 2
store <1 x half> %0, ptr %agg.result, align 2
ret void
}
define void @loadAndReturn__Float16_8(ptr dead_on_unwind noalias writable writeonly sret(<4 x half>) align 8 captures(none) initializes((0, 8)) %agg.result) {
; CHECK-LABEL: loadAndReturn__Float16_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global__Float16_8@GOT
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <4 x half>, ptr @global__Float16_8, align 8
store <4 x half> %0, ptr %agg.result, align 8
ret void
}
define void @loadAndReturn__Float16_16(ptr dead_on_unwind noalias writable writeonly sret(<8 x half>) align 16 captures(none) initializes((0, 16)) %agg.result) {
; CHECK-LABEL: loadAndReturn__Float16_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global__Float16_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <8 x half>, ptr @global__Float16_16, align 16
store <8 x half> %0, ptr %agg.result, align 16
ret void
}
define void @loadAndReturn__Float16_32(ptr dead_on_unwind noalias writable writeonly sret(<16 x half>) align 32 captures(none) initializes((0, 32)) %agg.result) {
; CHECK-LABEL: loadAndReturn__Float16_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global__Float16_32@GOT
; CHECK-NEXT: mvc 24(8,%r2), 24(%r1)
; CHECK-NEXT: mvc 16(8,%r2), 16(%r1)
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <16 x half>, ptr @global__Float16_32, align 32
store <16 x half> %0, ptr %agg.result, align 32
ret void
}
define void @loadAndReturn_float_4(ptr dead_on_unwind noalias writable writeonly sret(<1 x float>) align 4 captures(none) initializes((0, 4)) %agg.result) {
; CHECK-LABEL: loadAndReturn_float_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_float_4@GOT
; CHECK-NEXT: mvc 0(4,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x float>, ptr @global_float_4, align 4
store <1 x float> %0, ptr %agg.result, align 4
ret void
}
define void @loadAndReturn_float_8(ptr dead_on_unwind noalias writable writeonly sret(<2 x float>) align 8 captures(none) initializes((0, 8)) %agg.result) {
; CHECK-LABEL: loadAndReturn_float_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_float_8@GOT
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <2 x float>, ptr @global_float_8, align 8
store <2 x float> %0, ptr %agg.result, align 8
ret void
}
define void @loadAndReturn_float_16(ptr dead_on_unwind noalias writable writeonly sret(<4 x float>) align 16 captures(none) initializes((0, 16)) %agg.result) {
; CHECK-LABEL: loadAndReturn_float_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_float_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <4 x float>, ptr @global_float_16, align 16
store <4 x float> %0, ptr %agg.result, align 16
ret void
}
define void @loadAndReturn_double_8(ptr dead_on_unwind noalias writable writeonly sret(<1 x double>) align 8 captures(none) initializes((0, 8)) %agg.result) {
; CHECK-LABEL: loadAndReturn_double_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_double_8@GOT
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x double>, ptr @global_double_8, align 8
store <1 x double> %0, ptr %agg.result, align 8
ret void
}
define void @loadAndReturn_double_16(ptr dead_on_unwind noalias writable writeonly sret(<2 x double>) align 16 captures(none) initializes((0, 16)) %agg.result) {
; CHECK-LABEL: loadAndReturn_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_double_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <2 x double>, ptr @global_double_16, align 16
store <2 x double> %0, ptr %agg.result, align 16
ret void
}
define void @loadAndReturn_double_32(ptr dead_on_unwind noalias writable writeonly sret(<4 x double>) align 32 captures(none) initializes((0, 32)) %agg.result) {
; CHECK-LABEL: loadAndReturn_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_double_32@GOT
; CHECK-NEXT: mvc 24(8,%r2), 24(%r1)
; CHECK-NEXT: mvc 16(8,%r2), 16(%r1)
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <4 x double>, ptr @global_double_32, align 32
store <4 x double> %0, ptr %agg.result, align 32
ret void
}
define void @loadAndReturn_long_double_16(ptr dead_on_unwind noalias writable writeonly sret(<1 x fp128>) align 16 captures(none) initializes((0, 16)) %agg.result) {
; CHECK-LABEL: loadAndReturn_long_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_long_double_16@GOT
; CHECK-NEXT: mvc 0(16,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x fp128>, ptr @global_long_double_16, align 16
store <1 x fp128> %0, ptr %agg.result, align 16
ret void
}
define void @loadAndReturn_long_double_32(ptr dead_on_unwind noalias writable writeonly sret(<2 x fp128>) align 32 captures(none) initializes((0, 32)) %agg.result) {
; CHECK-LABEL: loadAndReturn_long_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_long_double_32@GOT
; CHECK-NEXT: mvc 16(16,%r2), 16(%r1)
; CHECK-NEXT: mvc 0(16,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <2 x fp128>, ptr @global_long_double_32, align 32
store <2 x fp128> %0, ptr %agg.result, align 32
ret void
}
define void @loadAndPass_char_1() {
; CHECK-LABEL: loadAndPass_char_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: lgrl %r1, global_char_1@GOT
; CHECK-NEXT: mvc 167(1,%r15), 0(%r1)
; CHECK-NEXT: la %r2, 167(%r15)
; CHECK-NEXT: brasl %r14, passCallee_char_1@PLT
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <1 x i8>, align 1
%0 = load <1 x i8>, ptr @global_char_1, align 2
store <1 x i8> %0, ptr %byval-temp, align 1
call void @passCallee_char_1(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_char_1(ptr noundef dead_on_return)
define void @loadAndPass_char_8() {
; CHECK-LABEL: loadAndPass_char_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: lgrl %r1, global_char_8@GOT
; CHECK-NEXT: mvc 160(8,%r15), 0(%r1)
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, passCallee_char_8@PLT
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <8 x i8>, align 8
%0 = load <8 x i8>, ptr @global_char_8, align 8
store <8 x i8> %0, ptr %byval-temp, align 8
call void @passCallee_char_8(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_char_8(ptr noundef dead_on_return)
define void @loadAndPass_char_16() {
; CHECK-LABEL: loadAndPass_char_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r2, 168(%r1)
; CHECK-NEXT: nill %r2, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global_char_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee_char_16@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <16 x i8>, align 16
%0 = load <16 x i8>, ptr @global_char_16, align 16
store <16 x i8> %0, ptr %byval-temp, align 16
call void @passCallee_char_16(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_char_16(ptr noundef dead_on_return)
define void @loadAndPass_char_32() {
; CHECK-LABEL: loadAndPass_char_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -56
; CHECK-NEXT: la %r2, 184(%r1)
; CHECK-NEXT: nill %r2, 65504
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global_char_32@GOT
; CHECK-NEXT: mvc 24(8,%r2), 24(%r1)
; CHECK-NEXT: mvc 16(8,%r2), 16(%r1)
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee_char_32@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <32 x i8>, align 32
%0 = load <32 x i8>, ptr @global_char_32, align 32
store <32 x i8> %0, ptr %byval-temp, align 32
call void @passCallee_char_32(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_char_32(ptr noundef dead_on_return)
define void @loadAndPass_short_2() {
; CHECK-LABEL: loadAndPass_short_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: lgrl %r1, global_short_2@GOT
; CHECK-NEXT: mvc 166(2,%r15), 0(%r1)
; CHECK-NEXT: la %r2, 166(%r15)
; CHECK-NEXT: brasl %r14, passCallee_short_2@PLT
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <1 x i16>, align 2
%0 = load <1 x i16>, ptr @global_short_2, align 2
store <1 x i16> %0, ptr %byval-temp, align 2
call void @passCallee_short_2(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_short_2(ptr noundef dead_on_return)
define void @loadAndPass_short_8() {
; CHECK-LABEL: loadAndPass_short_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: lgrl %r1, global_short_8@GOT
; CHECK-NEXT: mvc 160(8,%r15), 0(%r1)
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, passCallee_short_8@PLT
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <4 x i16>, align 8
%0 = load <4 x i16>, ptr @global_short_8, align 8
store <4 x i16> %0, ptr %byval-temp, align 8
call void @passCallee_short_8(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_short_8(ptr noundef dead_on_return)
define void @loadAndPass_short_16() {
; CHECK-LABEL: loadAndPass_short_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r2, 168(%r1)
; CHECK-NEXT: nill %r2, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global_short_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee_short_16@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <8 x i16>, align 16
%0 = load <8 x i16>, ptr @global_short_16, align 16
store <8 x i16> %0, ptr %byval-temp, align 16
call void @passCallee_short_16(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_short_16(ptr noundef dead_on_return)
define void @loadAndPass_int_4() {
; CHECK-LABEL: loadAndPass_int_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: lgrl %r1, global_int_4@GOT
; CHECK-NEXT: mvc 164(4,%r15), 0(%r1)
; CHECK-NEXT: la %r2, 164(%r15)
; CHECK-NEXT: brasl %r14, passCallee_int_4@PLT
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <1 x i32>, align 4
%0 = load <1 x i32>, ptr @global_int_4, align 4
store <1 x i32> %0, ptr %byval-temp, align 4
call void @passCallee_int_4(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_int_4(ptr noundef dead_on_return)
define void @loadAndPass_int_8() {
; CHECK-LABEL: loadAndPass_int_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: lgrl %r1, global_int_8@GOT
; CHECK-NEXT: mvc 160(8,%r15), 0(%r1)
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, passCallee_int_8@PLT
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <2 x i32>, align 8
%0 = load <2 x i32>, ptr @global_int_8, align 8
store <2 x i32> %0, ptr %byval-temp, align 8
call void @passCallee_int_8(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_int_8(ptr noundef dead_on_return)
define void @loadAndPass_int_16() {
; CHECK-LABEL: loadAndPass_int_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r2, 168(%r1)
; CHECK-NEXT: nill %r2, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global_int_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee_int_16@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <4 x i32>, align 16
%0 = load <4 x i32>, ptr @global_int_16, align 16
store <4 x i32> %0, ptr %byval-temp, align 16
call void @passCallee_int_16(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_int_16(ptr noundef dead_on_return)
define void @loadAndPass_int_32() {
; CHECK-LABEL: loadAndPass_int_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -56
; CHECK-NEXT: la %r2, 184(%r1)
; CHECK-NEXT: nill %r2, 65504
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global_int_32@GOT
; CHECK-NEXT: mvc 24(8,%r2), 24(%r1)
; CHECK-NEXT: mvc 16(8,%r2), 16(%r1)
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee_int_32@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <8 x i32>, align 32
%0 = load <8 x i32>, ptr @global_int_32, align 32
store <8 x i32> %0, ptr %byval-temp, align 32
call void @passCallee_int_32(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_int_32(ptr noundef dead_on_return)
define void @loadAndPass_long_8() {
; CHECK-LABEL: loadAndPass_long_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: lgrl %r1, global_long_8@GOT
; CHECK-NEXT: mvc 160(8,%r15), 0(%r1)
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, passCallee_long_8@PLT
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <1 x i64>, align 8
%0 = load <1 x i64>, ptr @global_long_8, align 8
store <1 x i64> %0, ptr %byval-temp, align 8
call void @passCallee_long_8(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_long_8(ptr noundef dead_on_return)
define void @loadAndPass_long_16() {
; CHECK-LABEL: loadAndPass_long_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r2, 168(%r1)
; CHECK-NEXT: nill %r2, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global_long_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee_long_16@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <2 x i64>, align 16
%0 = load <2 x i64>, ptr @global_long_16, align 16
store <2 x i64> %0, ptr %byval-temp, align 16
call void @passCallee_long_16(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_long_16(ptr noundef dead_on_return)
define void @loadAndPass___int128_16() {
; CHECK-LABEL: loadAndPass___int128_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r2, 168(%r1)
; CHECK-NEXT: nill %r2, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global___int128_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee___int128_16@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <1 x i128>, align 16
%0 = load <1 x i128>, ptr @global___int128_16, align 16
store <1 x i128> %0, ptr %byval-temp, align 16
call void @passCallee___int128_16(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee___int128_16(ptr noundef dead_on_return)
define void @loadAndPass___int128_32() {
; CHECK-LABEL: loadAndPass___int128_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -56
; CHECK-NEXT: la %r2, 184(%r1)
; CHECK-NEXT: nill %r2, 65504
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global___int128_32@GOT
; CHECK-NEXT: mvc 24(8,%r2), 24(%r1)
; CHECK-NEXT: mvc 16(8,%r2), 16(%r1)
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee___int128_32@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <2 x i128>, align 32
%0 = load <2 x i128>, ptr @global___int128_32, align 32
store <2 x i128> %0, ptr %byval-temp, align 32
call void @passCallee___int128_32(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee___int128_32(ptr noundef dead_on_return)
define void @loadAndPass__Float16_2() {
; CHECK-LABEL: loadAndPass__Float16_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: lgrl %r1, global__Float16_2@GOT
; CHECK-NEXT: lgh %r0, 0(%r1)
; CHECK-NEXT: sllg %r0, %r0, 48
; CHECK-NEXT: ldgr %f0, %r0
; CHECK-NEXT: lgdr %r0, %f0
; CHECK-NEXT: srlg %r0, %r0, 48
; CHECK-NEXT: la %r2, 166(%r15)
; CHECK-NEXT: sth %r0, 166(%r15)
; CHECK-NEXT: brasl %r14, passCallee__Float16_2@PLT
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <1 x half>, align 2
%0 = load <1 x half>, ptr @global__Float16_2, align 2
store <1 x half> %0, ptr %byval-temp, align 2
call void @passCallee__Float16_2(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee__Float16_2(ptr noundef dead_on_return)
define void @loadAndPass__Float16_8() {
; CHECK-LABEL: loadAndPass__Float16_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: lgrl %r1, global__Float16_8@GOT
; CHECK-NEXT: mvc 160(8,%r15), 0(%r1)
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, passCallee__Float16_8@PLT
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <4 x half>, align 8
%0 = load <4 x half>, ptr @global__Float16_8, align 8
store <4 x half> %0, ptr %byval-temp, align 8
call void @passCallee__Float16_8(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee__Float16_8(ptr noundef dead_on_return)
define void @loadAndPass__Float16_16() {
; CHECK-LABEL: loadAndPass__Float16_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r2, 168(%r1)
; CHECK-NEXT: nill %r2, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global__Float16_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee__Float16_16@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <8 x half>, align 16
%0 = load <8 x half>, ptr @global__Float16_16, align 16
store <8 x half> %0, ptr %byval-temp, align 16
call void @passCallee__Float16_16(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee__Float16_16(ptr noundef dead_on_return)
define void @loadAndPass__Float16_32() {
; CHECK-LABEL: loadAndPass__Float16_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -56
; CHECK-NEXT: la %r2, 184(%r1)
; CHECK-NEXT: nill %r2, 65504
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global__Float16_32@GOT
; CHECK-NEXT: mvc 24(8,%r2), 24(%r1)
; CHECK-NEXT: mvc 16(8,%r2), 16(%r1)
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee__Float16_32@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <16 x half>, align 32
%0 = load <16 x half>, ptr @global__Float16_32, align 32
store <16 x half> %0, ptr %byval-temp, align 32
call void @passCallee__Float16_32(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee__Float16_32(ptr noundef dead_on_return)
define void @loadAndPass_float_4() {
; CHECK-LABEL: loadAndPass_float_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: lgrl %r1, global_float_4@GOT
; CHECK-NEXT: mvc 164(4,%r15), 0(%r1)
; CHECK-NEXT: la %r2, 164(%r15)
; CHECK-NEXT: brasl %r14, passCallee_float_4@PLT
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <1 x float>, align 4
%0 = load <1 x float>, ptr @global_float_4, align 4
store <1 x float> %0, ptr %byval-temp, align 4
call void @passCallee_float_4(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_float_4(ptr noundef dead_on_return)
define void @loadAndPass_float_8() {
; CHECK-LABEL: loadAndPass_float_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: lgrl %r1, global_float_8@GOT
; CHECK-NEXT: mvc 160(8,%r15), 0(%r1)
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, passCallee_float_8@PLT
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <2 x float>, align 8
%0 = load <2 x float>, ptr @global_float_8, align 8
store <2 x float> %0, ptr %byval-temp, align 8
call void @passCallee_float_8(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_float_8(ptr noundef dead_on_return)
define void @loadAndPass_float_16() {
; CHECK-LABEL: loadAndPass_float_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r2, 168(%r1)
; CHECK-NEXT: nill %r2, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global_float_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee_float_16@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <4 x float>, align 16
%0 = load <4 x float>, ptr @global_float_16, align 16
store <4 x float> %0, ptr %byval-temp, align 16
call void @passCallee_float_16(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_float_16(ptr noundef dead_on_return)
define void @loadAndPass_double_8() {
; CHECK-LABEL: loadAndPass_double_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: lgrl %r1, global_double_8@GOT
; CHECK-NEXT: mvc 160(8,%r15), 0(%r1)
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, passCallee_double_8@PLT
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <1 x double>, align 8
%0 = load <1 x double>, ptr @global_double_8, align 8
store <1 x double> %0, ptr %byval-temp, align 8
call void @passCallee_double_8(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_double_8(ptr noundef dead_on_return)
define void @loadAndPass_double_16() {
; CHECK-LABEL: loadAndPass_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r2, 168(%r1)
; CHECK-NEXT: nill %r2, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global_double_16@GOT
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee_double_16@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <2 x double>, align 16
%0 = load <2 x double>, ptr @global_double_16, align 16
store <2 x double> %0, ptr %byval-temp, align 16
call void @passCallee_double_16(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_double_16(ptr noundef dead_on_return)
define void @loadAndPass_double_32() {
; CHECK-LABEL: loadAndPass_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -56
; CHECK-NEXT: la %r2, 184(%r1)
; CHECK-NEXT: nill %r2, 65504
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global_double_32@GOT
; CHECK-NEXT: mvc 24(8,%r2), 24(%r1)
; CHECK-NEXT: mvc 16(8,%r2), 16(%r1)
; CHECK-NEXT: mvc 8(8,%r2), 8(%r1)
; CHECK-NEXT: mvc 0(8,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee_double_32@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <4 x double>, align 32
%0 = load <4 x double>, ptr @global_double_32, align 32
store <4 x double> %0, ptr %byval-temp, align 32
call void @passCallee_double_32(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_double_32(ptr noundef dead_on_return)
define void @loadAndPass_long_double_16() {
; CHECK-LABEL: loadAndPass_long_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r2, 168(%r1)
; CHECK-NEXT: nill %r2, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global_long_double_16@GOT
; CHECK-NEXT: mvc 0(16,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee_long_double_16@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <1 x fp128>, align 16
%0 = load <1 x fp128>, ptr @global_long_double_16, align 16
store <1 x fp128> %0, ptr %byval-temp, align 16
call void @passCallee_long_double_16(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_long_double_16(ptr noundef dead_on_return)
define void @loadAndPass_long_double_32() {
; CHECK-LABEL: loadAndPass_long_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -56
; CHECK-NEXT: la %r2, 184(%r1)
; CHECK-NEXT: nill %r2, 65504
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgrl %r1, global_long_double_32@GOT
; CHECK-NEXT: mvc 16(16,%r2), 16(%r1)
; CHECK-NEXT: mvc 0(16,%r2), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee_long_double_32@PLT
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <2 x fp128>, align 32
%0 = load <2 x fp128>, ptr @global_long_double_32, align 32
store <2 x fp128> %0, ptr %byval-temp, align 32
call void @passCallee_long_double_32(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_long_double_32(ptr noundef dead_on_return)
define void @receiveAndStore_char_1() {
; CHECK-LABEL: receiveAndStore_char_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: la %r2, 167(%r15)
; CHECK-NEXT: brasl %r14, retCallee_char_1@PLT
; CHECK-NEXT: lgrl %r1, global_char_1@GOT
; CHECK-NEXT: mvc 0(1,%r1), 167(%r15)
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <1 x i8>, align 1
call void @retCallee_char_1(ptr dead_on_unwind nonnull writable sret(<1 x i8>) align 1 %tmp)
%0 = load <1 x i8>, ptr %tmp, align 1
store <1 x i8> %0, ptr @global_char_1, align 2
ret void
}
declare void @retCallee_char_1(ptr dead_on_unwind writable sret(<1 x i8>) align 1)
define void @receiveAndStore_char_8() {
; CHECK-LABEL: receiveAndStore_char_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, retCallee_char_8@PLT
; CHECK-NEXT: lgrl %r1, global_char_8@GOT
; CHECK-NEXT: mvc 0(8,%r1), 160(%r15)
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <8 x i8>, align 8
call void @retCallee_char_8(ptr dead_on_unwind nonnull writable sret(<8 x i8>) align 8 %tmp)
%0 = load <8 x i8>, ptr %tmp, align 8
store <8 x i8> %0, ptr @global_char_8, align 8
ret void
}
declare void @retCallee_char_8(ptr dead_on_unwind writable sret(<8 x i8>) align 8)
define void @receiveAndStore_char_16() {
; CHECK-LABEL: receiveAndStore_char_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r13, 168(%r1)
; CHECK-NEXT: nill %r13, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee_char_16@PLT
; CHECK-NEXT: lgrl %r1, global_char_16@GOT
; CHECK-NEXT: mvc 8(8,%r1), 8(%r13)
; CHECK-NEXT: mvc 0(8,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <16 x i8>, align 16
call void @retCallee_char_16(ptr dead_on_unwind nonnull writable sret(<16 x i8>) align 16 %tmp)
%0 = load <16 x i8>, ptr %tmp, align 16
store <16 x i8> %0, ptr @global_char_16, align 16
ret void
}
declare void @retCallee_char_16(ptr dead_on_unwind writable sret(<16 x i8>) align 16)
define void @receiveAndStore_char_32() {
; CHECK-LABEL: receiveAndStore_char_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -56
; CHECK-NEXT: la %r13, 184(%r1)
; CHECK-NEXT: nill %r13, 65504
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee_char_32@PLT
; CHECK-NEXT: lgrl %r1, global_char_32@GOT
; CHECK-NEXT: mvc 24(8,%r1), 24(%r13)
; CHECK-NEXT: mvc 16(8,%r1), 16(%r13)
; CHECK-NEXT: mvc 8(8,%r1), 8(%r13)
; CHECK-NEXT: mvc 0(8,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <32 x i8>, align 32
call void @retCallee_char_32(ptr dead_on_unwind nonnull writable sret(<32 x i8>) align 32 %tmp)
%0 = load <32 x i8>, ptr %tmp, align 32
store <32 x i8> %0, ptr @global_char_32, align 32
ret void
}
declare void @retCallee_char_32(ptr dead_on_unwind writable sret(<32 x i8>) align 32)
define void @receiveAndStore_short_2() {
; CHECK-LABEL: receiveAndStore_short_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: la %r2, 166(%r15)
; CHECK-NEXT: brasl %r14, retCallee_short_2@PLT
; CHECK-NEXT: lgrl %r1, global_short_2@GOT
; CHECK-NEXT: mvc 0(2,%r1), 166(%r15)
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <1 x i16>, align 2
call void @retCallee_short_2(ptr dead_on_unwind nonnull writable sret(<1 x i16>) align 2 %tmp)
%0 = load <1 x i16>, ptr %tmp, align 2
store <1 x i16> %0, ptr @global_short_2, align 2
ret void
}
declare void @retCallee_short_2(ptr dead_on_unwind writable sret(<1 x i16>) align 2)
define void @receiveAndStore_short_8() {
; CHECK-LABEL: receiveAndStore_short_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, retCallee_short_8@PLT
; CHECK-NEXT: lgrl %r1, global_short_8@GOT
; CHECK-NEXT: mvc 0(8,%r1), 160(%r15)
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <4 x i16>, align 8
call void @retCallee_short_8(ptr dead_on_unwind nonnull writable sret(<4 x i16>) align 8 %tmp)
%0 = load <4 x i16>, ptr %tmp, align 8
store <4 x i16> %0, ptr @global_short_8, align 8
ret void
}
declare void @retCallee_short_8(ptr dead_on_unwind writable sret(<4 x i16>) align 8)
define void @receiveAndStore_short_16() {
; CHECK-LABEL: receiveAndStore_short_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r13, 168(%r1)
; CHECK-NEXT: nill %r13, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee_short_16@PLT
; CHECK-NEXT: lgrl %r1, global_short_16@GOT
; CHECK-NEXT: mvc 8(8,%r1), 8(%r13)
; CHECK-NEXT: mvc 0(8,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <8 x i16>, align 16
call void @retCallee_short_16(ptr dead_on_unwind nonnull writable sret(<8 x i16>) align 16 %tmp)
%0 = load <8 x i16>, ptr %tmp, align 16
store <8 x i16> %0, ptr @global_short_16, align 16
ret void
}
declare void @retCallee_short_16(ptr dead_on_unwind writable sret(<8 x i16>) align 16)
define void @receiveAndStore_int_4() {
; CHECK-LABEL: receiveAndStore_int_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: la %r2, 164(%r15)
; CHECK-NEXT: brasl %r14, retCallee_int_4@PLT
; CHECK-NEXT: lgrl %r1, global_int_4@GOT
; CHECK-NEXT: mvc 0(4,%r1), 164(%r15)
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <1 x i32>, align 4
call void @retCallee_int_4(ptr dead_on_unwind nonnull writable sret(<1 x i32>) align 4 %tmp)
%0 = load <1 x i32>, ptr %tmp, align 4
store <1 x i32> %0, ptr @global_int_4, align 4
ret void
}
declare void @retCallee_int_4(ptr dead_on_unwind writable sret(<1 x i32>) align 4)
define void @receiveAndStore_int_8() {
; CHECK-LABEL: receiveAndStore_int_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, retCallee_int_8@PLT
; CHECK-NEXT: lgrl %r1, global_int_8@GOT
; CHECK-NEXT: mvc 0(8,%r1), 160(%r15)
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <2 x i32>, align 8
call void @retCallee_int_8(ptr dead_on_unwind nonnull writable sret(<2 x i32>) align 8 %tmp)
%0 = load <2 x i32>, ptr %tmp, align 8
store <2 x i32> %0, ptr @global_int_8, align 8
ret void
}
declare void @retCallee_int_8(ptr dead_on_unwind writable sret(<2 x i32>) align 8)
define void @receiveAndStore_int_16() {
; CHECK-LABEL: receiveAndStore_int_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r13, 168(%r1)
; CHECK-NEXT: nill %r13, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee_int_16@PLT
; CHECK-NEXT: lgrl %r1, global_int_16@GOT
; CHECK-NEXT: mvc 8(8,%r1), 8(%r13)
; CHECK-NEXT: mvc 0(8,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <4 x i32>, align 16
call void @retCallee_int_16(ptr dead_on_unwind nonnull writable sret(<4 x i32>) align 16 %tmp)
%0 = load <4 x i32>, ptr %tmp, align 16
store <4 x i32> %0, ptr @global_int_16, align 16
ret void
}
declare void @retCallee_int_16(ptr dead_on_unwind writable sret(<4 x i32>) align 16)
define void @receiveAndStore_int_32() {
; CHECK-LABEL: receiveAndStore_int_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -56
; CHECK-NEXT: la %r13, 184(%r1)
; CHECK-NEXT: nill %r13, 65504
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee_int_32@PLT
; CHECK-NEXT: lgrl %r1, global_int_32@GOT
; CHECK-NEXT: mvc 24(8,%r1), 24(%r13)
; CHECK-NEXT: mvc 16(8,%r1), 16(%r13)
; CHECK-NEXT: mvc 8(8,%r1), 8(%r13)
; CHECK-NEXT: mvc 0(8,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <8 x i32>, align 32
call void @retCallee_int_32(ptr dead_on_unwind nonnull writable sret(<8 x i32>) align 32 %tmp)
%0 = load <8 x i32>, ptr %tmp, align 32
store <8 x i32> %0, ptr @global_int_32, align 32
ret void
}
declare void @retCallee_int_32(ptr dead_on_unwind writable sret(<8 x i32>) align 32)
define void @receiveAndStore_long_8() {
; CHECK-LABEL: receiveAndStore_long_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, retCallee_long_8@PLT
; CHECK-NEXT: lgrl %r1, global_long_8@GOT
; CHECK-NEXT: mvc 0(8,%r1), 160(%r15)
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <1 x i64>, align 8
call void @retCallee_long_8(ptr dead_on_unwind nonnull writable sret(<1 x i64>) align 8 %tmp)
%0 = load <1 x i64>, ptr %tmp, align 8
store <1 x i64> %0, ptr @global_long_8, align 8
ret void
}
declare void @retCallee_long_8(ptr dead_on_unwind writable sret(<1 x i64>) align 8)
define void @receiveAndStore_long_16() {
; CHECK-LABEL: receiveAndStore_long_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r13, 168(%r1)
; CHECK-NEXT: nill %r13, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee_long_16@PLT
; CHECK-NEXT: lgrl %r1, global_long_16@GOT
; CHECK-NEXT: mvc 8(8,%r1), 8(%r13)
; CHECK-NEXT: mvc 0(8,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <2 x i64>, align 16
call void @retCallee_long_16(ptr dead_on_unwind nonnull writable sret(<2 x i64>) align 16 %tmp)
%0 = load <2 x i64>, ptr %tmp, align 16
store <2 x i64> %0, ptr @global_long_16, align 16
ret void
}
declare void @retCallee_long_16(ptr dead_on_unwind writable sret(<2 x i64>) align 16)
define void @receiveAndStore___int128_16() {
; CHECK-LABEL: receiveAndStore___int128_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r13, 168(%r1)
; CHECK-NEXT: nill %r13, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee___int128_16@PLT
; CHECK-NEXT: lgrl %r1, global___int128_16@GOT
; CHECK-NEXT: mvc 8(8,%r1), 8(%r13)
; CHECK-NEXT: mvc 0(8,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <1 x i128>, align 16
call void @retCallee___int128_16(ptr dead_on_unwind nonnull writable sret(<1 x i128>) align 16 %tmp)
%0 = load <1 x i128>, ptr %tmp, align 16
store <1 x i128> %0, ptr @global___int128_16, align 16
ret void
}
declare void @retCallee___int128_16(ptr dead_on_unwind writable sret(<1 x i128>) align 16)
define void @receiveAndStore___int128_32() {
; CHECK-LABEL: receiveAndStore___int128_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -56
; CHECK-NEXT: la %r13, 184(%r1)
; CHECK-NEXT: nill %r13, 65504
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee___int128_32@PLT
; CHECK-NEXT: lgrl %r1, global___int128_32@GOT
; CHECK-NEXT: mvc 24(8,%r1), 24(%r13)
; CHECK-NEXT: mvc 16(8,%r1), 16(%r13)
; CHECK-NEXT: mvc 8(8,%r1), 8(%r13)
; CHECK-NEXT: mvc 0(8,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <2 x i128>, align 32
call void @retCallee___int128_32(ptr dead_on_unwind nonnull writable sret(<2 x i128>) align 32 %tmp)
%0 = load <2 x i128>, ptr %tmp, align 32
store <2 x i128> %0, ptr @global___int128_32, align 32
ret void
}
declare void @retCallee___int128_32(ptr dead_on_unwind writable sret(<2 x i128>) align 32)
define void @receiveAndStore__Float16_2() {
; CHECK-LABEL: receiveAndStore__Float16_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: la %r2, 166(%r15)
; CHECK-NEXT: brasl %r14, retCallee__Float16_2@PLT
; CHECK-NEXT: lgh %r0, 166(%r15)
; CHECK-NEXT: sllg %r0, %r0, 48
; CHECK-NEXT: lgrl %r1, global__Float16_2@GOT
; CHECK-NEXT: ldgr %f0, %r0
; CHECK-NEXT: lgdr %r0, %f0
; CHECK-NEXT: srlg %r0, %r0, 48
; CHECK-NEXT: sth %r0, 0(%r1)
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <1 x half>, align 2
call void @retCallee__Float16_2(ptr dead_on_unwind nonnull writable sret(<1 x half>) align 2 %tmp)
%0 = load <1 x half>, ptr %tmp, align 2
store <1 x half> %0, ptr @global__Float16_2, align 2
ret void
}
declare void @retCallee__Float16_2(ptr dead_on_unwind writable sret(<1 x half>) align 2)
define void @receiveAndStore__Float16_8() {
; CHECK-LABEL: receiveAndStore__Float16_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, retCallee__Float16_8@PLT
; CHECK-NEXT: lgrl %r1, global__Float16_8@GOT
; CHECK-NEXT: mvc 0(8,%r1), 160(%r15)
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <4 x half>, align 8
call void @retCallee__Float16_8(ptr dead_on_unwind nonnull writable sret(<4 x half>) align 8 %tmp)
%0 = load <4 x half>, ptr %tmp, align 8
store <4 x half> %0, ptr @global__Float16_8, align 8
ret void
}
declare void @retCallee__Float16_8(ptr dead_on_unwind writable sret(<4 x half>) align 8)
define void @receiveAndStore__Float16_16() {
; CHECK-LABEL: receiveAndStore__Float16_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r13, 168(%r1)
; CHECK-NEXT: nill %r13, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee__Float16_16@PLT
; CHECK-NEXT: lgrl %r1, global__Float16_16@GOT
; CHECK-NEXT: mvc 8(8,%r1), 8(%r13)
; CHECK-NEXT: mvc 0(8,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <8 x half>, align 16
call void @retCallee__Float16_16(ptr dead_on_unwind nonnull writable sret(<8 x half>) align 16 %tmp)
%0 = load <8 x half>, ptr %tmp, align 16
store <8 x half> %0, ptr @global__Float16_16, align 16
ret void
}
declare void @retCallee__Float16_16(ptr dead_on_unwind writable sret(<8 x half>) align 16)
define void @receiveAndStore__Float16_32() {
; CHECK-LABEL: receiveAndStore__Float16_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -56
; CHECK-NEXT: la %r13, 184(%r1)
; CHECK-NEXT: nill %r13, 65504
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee__Float16_32@PLT
; CHECK-NEXT: lgrl %r1, global__Float16_32@GOT
; CHECK-NEXT: mvc 24(8,%r1), 24(%r13)
; CHECK-NEXT: mvc 16(8,%r1), 16(%r13)
; CHECK-NEXT: mvc 8(8,%r1), 8(%r13)
; CHECK-NEXT: mvc 0(8,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <16 x half>, align 32
call void @retCallee__Float16_32(ptr dead_on_unwind nonnull writable sret(<16 x half>) align 32 %tmp)
%0 = load <16 x half>, ptr %tmp, align 32
store <16 x half> %0, ptr @global__Float16_32, align 32
ret void
}
declare void @retCallee__Float16_32(ptr dead_on_unwind writable sret(<16 x half>) align 32)
define void @receiveAndStore_float_4() {
; CHECK-LABEL: receiveAndStore_float_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: la %r2, 164(%r15)
; CHECK-NEXT: brasl %r14, retCallee_float_4@PLT
; CHECK-NEXT: lgrl %r1, global_float_4@GOT
; CHECK-NEXT: mvc 0(4,%r1), 164(%r15)
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <1 x float>, align 4
call void @retCallee_float_4(ptr dead_on_unwind nonnull writable sret(<1 x float>) align 4 %tmp)
%0 = load <1 x float>, ptr %tmp, align 4
store <1 x float> %0, ptr @global_float_4, align 4
ret void
}
declare void @retCallee_float_4(ptr dead_on_unwind writable sret(<1 x float>) align 4)
define void @receiveAndStore_float_8() {
; CHECK-LABEL: receiveAndStore_float_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, retCallee_float_8@PLT
; CHECK-NEXT: lgrl %r1, global_float_8@GOT
; CHECK-NEXT: mvc 0(8,%r1), 160(%r15)
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <2 x float>, align 8
call void @retCallee_float_8(ptr dead_on_unwind nonnull writable sret(<2 x float>) align 8 %tmp)
%0 = load <2 x float>, ptr %tmp, align 8
store <2 x float> %0, ptr @global_float_8, align 8
ret void
}
declare void @retCallee_float_8(ptr dead_on_unwind writable sret(<2 x float>) align 8)
define void @receiveAndStore_float_16() {
; CHECK-LABEL: receiveAndStore_float_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r13, 168(%r1)
; CHECK-NEXT: nill %r13, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee_float_16@PLT
; CHECK-NEXT: lgrl %r1, global_float_16@GOT
; CHECK-NEXT: mvc 8(8,%r1), 8(%r13)
; CHECK-NEXT: mvc 0(8,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <4 x float>, align 16
call void @retCallee_float_16(ptr dead_on_unwind nonnull writable sret(<4 x float>) align 16 %tmp)
%0 = load <4 x float>, ptr %tmp, align 16
store <4 x float> %0, ptr @global_float_16, align 16
ret void
}
declare void @retCallee_float_16(ptr dead_on_unwind writable sret(<4 x float>) align 16)
define void @receiveAndStore_double_8() {
; CHECK-LABEL: receiveAndStore_double_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, retCallee_double_8@PLT
; CHECK-NEXT: lgrl %r1, global_double_8@GOT
; CHECK-NEXT: mvc 0(8,%r1), 160(%r15)
; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <1 x double>, align 8
call void @retCallee_double_8(ptr dead_on_unwind nonnull writable sret(<1 x double>) align 8 %tmp)
%0 = load <1 x double>, ptr %tmp, align 8
store <1 x double> %0, ptr @global_double_8, align 8
ret void
}
declare void @retCallee_double_8(ptr dead_on_unwind writable sret(<1 x double>) align 8)
define void @receiveAndStore_double_16() {
; CHECK-LABEL: receiveAndStore_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r13, 168(%r1)
; CHECK-NEXT: nill %r13, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee_double_16@PLT
; CHECK-NEXT: lgrl %r1, global_double_16@GOT
; CHECK-NEXT: mvc 8(8,%r1), 8(%r13)
; CHECK-NEXT: mvc 0(8,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <2 x double>, align 16
call void @retCallee_double_16(ptr dead_on_unwind nonnull writable sret(<2 x double>) align 16 %tmp)
%0 = load <2 x double>, ptr %tmp, align 16
store <2 x double> %0, ptr @global_double_16, align 16
ret void
}
declare void @retCallee_double_16(ptr dead_on_unwind writable sret(<2 x double>) align 16)
define void @receiveAndStore_double_32() {
; CHECK-LABEL: receiveAndStore_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -56
; CHECK-NEXT: la %r13, 184(%r1)
; CHECK-NEXT: nill %r13, 65504
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee_double_32@PLT
; CHECK-NEXT: lgrl %r1, global_double_32@GOT
; CHECK-NEXT: mvc 24(8,%r1), 24(%r13)
; CHECK-NEXT: mvc 16(8,%r1), 16(%r13)
; CHECK-NEXT: mvc 8(8,%r1), 8(%r13)
; CHECK-NEXT: mvc 0(8,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <4 x double>, align 32
call void @retCallee_double_32(ptr dead_on_unwind nonnull writable sret(<4 x double>) align 32 %tmp)
%0 = load <4 x double>, ptr %tmp, align 32
store <4 x double> %0, ptr @global_double_32, align 32
ret void
}
declare void @retCallee_double_32(ptr dead_on_unwind writable sret(<4 x double>) align 32)
define void @receiveAndStore_long_double_16() {
; CHECK-LABEL: receiveAndStore_long_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -24
; CHECK-NEXT: la %r13, 168(%r1)
; CHECK-NEXT: nill %r13, 65520
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee_long_double_16@PLT
; CHECK-NEXT: lgrl %r1, global_long_double_16@GOT
; CHECK-NEXT: mvc 0(16,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <1 x fp128>, align 16
call void @retCallee_long_double_16(ptr dead_on_unwind nonnull writable sret(<1 x fp128>) align 16 %tmp)
%0 = load <1 x fp128>, ptr %tmp, align 16
store <1 x fp128> %0, ptr @global_long_double_16, align 16
ret void
}
declare void @retCallee_long_double_16(ptr dead_on_unwind writable sret(<1 x fp128>) align 16)
define void @receiveAndStore_long_double_32() {
; CHECK-LABEL: receiveAndStore_long_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
; CHECK-NEXT: .cfi_offset %r11, -72
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
; CHECK-NEXT: lgr %r1, %r15
; CHECK-NEXT: aghi %r1, -56
; CHECK-NEXT: la %r13, 184(%r1)
; CHECK-NEXT: nill %r13, 65504
; CHECK-NEXT: lgr %r15, %r1
; CHECK-NEXT: lgr %r2, %r13
; CHECK-NEXT: brasl %r14, retCallee_long_double_32@PLT
; CHECK-NEXT: lgrl %r1, global_long_double_32@GOT
; CHECK-NEXT: mvc 16(16,%r1), 16(%r13)
; CHECK-NEXT: mvc 0(16,%r1), 0(%r13)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <2 x fp128>, align 32
call void @retCallee_long_double_32(ptr dead_on_unwind nonnull writable sret(<2 x fp128>) align 32 %tmp)
%0 = load <2 x fp128>, ptr %tmp, align 32
store <2 x fp128> %0, ptr @global_long_double_32, align 32
ret void
}
declare void @retCallee_long_double_32(ptr dead_on_unwind writable sret(<2 x fp128>) align 32)
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