8cf43aebc6
When unable to widen a vector load/store we can replace the operation with a masked variant. Support for extending loads largely came for free hence its inclusion, but truncating stores require more work. Fixes https://github.com/llvm/llvm-project/issues/159995
50 lines
1.7 KiB
LLVM
50 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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; This would assert because VE specified that all setcc
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; nodes (even with vector operands) return a scalar value.
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define <4 x i8> @udiv_by_minus_one(<4 x i8> %x) {
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; CHECK-LABEL: udiv_by_minus_one:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s4, %s0, (56)0
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; CHECK-NEXT: and %s1, %s1, (56)0
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; CHECK-NEXT: and %s2, %s2, (56)0
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; CHECK-NEXT: and %s3, %s3, (56)0
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; CHECK-NEXT: or %s0, 0, (0)1
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; CHECK-NEXT: cmpu.w %s5, %s3, (56)0
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; CHECK-NEXT: or %s3, 0, (0)1
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; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s5
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; CHECK-NEXT: cmpu.w %s5, %s2, (56)0
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; CHECK-NEXT: or %s2, 0, (0)1
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; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s5
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; CHECK-NEXT: cmpu.w %s5, %s1, (56)0
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s5
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; CHECK-NEXT: cmpu.w %s4, %s4, (56)0
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; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s4
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; CHECK-NEXT: b.l.t (, %s10)
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%r = udiv <4 x i8> %x, <i8 255, i8 255, i8 255, i8 255>
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ret <4 x i8> %r
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}
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define <4 x i8> @urem_by_minus_one(<4 x i8> %x) {
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; CHECK-LABEL: urem_by_minus_one:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s4, %s0, (56)0
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; CHECK-NEXT: and %s5, %s1, (56)0
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; CHECK-NEXT: and %s6, %s2, (56)0
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; CHECK-NEXT: and %s7, %s3, (56)0
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; CHECK-NEXT: cmpu.w %s7, %s7, (56)0
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; CHECK-NEXT: cmov.w.eq %s3, (0)1, %s7
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; CHECK-NEXT: cmpu.w %s6, %s6, (56)0
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; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s6
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; CHECK-NEXT: cmpu.w %s5, %s5, (56)0
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; CHECK-NEXT: cmov.w.eq %s1, (0)1, %s5
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; CHECK-NEXT: cmpu.w %s4, %s4, (56)0
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; CHECK-NEXT: cmov.w.eq %s0, (0)1, %s4
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; CHECK-NEXT: b.l.t (, %s10)
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%r = urem <4 x i8> %x, <i8 255, i8 255, i8 255, i8 255>
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ret <4 x i8> %r
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}
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