ca78b6ed21
The debug messages are difficult to follow, because it is not printing which loops it is dealing with. This adds loop names to various debug messages so it's easier to see which loops it is accepting, rejecting, etc.
198 lines
6.4 KiB
LLVM
198 lines
6.4 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt < %s -passes=loop-interchange -verify-dom-info -verify-loop-info \
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; RUN: -disable-output -debug 2>&1 | FileCheck %s
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@a = dso_local global [256 x [256 x float]] zeroinitializer, align 4
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@b = dso_local global [20 x [20 x [20 x i32]]] zeroinitializer, align 4
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;; for (int n = 0; n < 100; ++n)
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;; for (int i = 0; i < 256; ++i)
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;; for (int j = 1; j < 256; ++j)
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;; a[j - 1][i] += a[j][i];
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;;
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;; The direction vector of `a` is [* = <]. We can interchange the innermost
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;; two loops, The direction vector after interchanging will be [* < =].
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; CHECK: Dependency matrix before interchange:
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; CHECK-NEXT: * = <
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; CHECK-NEXT: * = =
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; CHECK-NEXT: Processing InnerLoopId = 2 and OuterLoopId = 1
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; CHECK-NEXT: Checking if loops 'for.i.header' and 'for.j' are tightly nested
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; CHECK-NEXT: Checking instructions in Loop header and Loop latch
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; CHECK-NEXT: Loops are perfectly nested
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; CHECK-NEXT: Loops 'for.i.header' and 'for.j' are legal to interchange
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define void @all_eq_lt() {
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entry:
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br label %for.n.header
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for.n.header:
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%n = phi i32 [ 0, %entry ], [ %n.inc, %for.n.latch ]
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br label %for.i.header
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for.i.header:
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%i = phi i32 [ 0, %for.n.header ], [ %i.inc, %for.i.latch ]
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br label %for.j
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for.j:
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%j = phi i32 [ 1, %for.i.header ], [ %j.inc, %for.j ]
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%j.dec = sub nsw i32 %j, 1
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%idx.store = getelementptr inbounds [256 x [256 x float]], ptr @a, i32 0, i32 %j.dec, i32 %i
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%idx.load = getelementptr inbounds [256 x [256 x float]], ptr @a, i32 0, i32 %j, i32 %i
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%0 = load float, ptr %idx.load, align 4
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%1 = load float, ptr %idx.store, align 4
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%add = fadd fast float %0, %1
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store float %add, ptr %idx.store, align 4
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%j.inc = add nuw nsw i32 %j, 1
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%cmp.j = icmp slt i32 %j.inc, 256
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br i1 %cmp.j, label %for.j, label %for.i.latch
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for.i.latch:
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%i.inc = add nuw nsw i32 %i, 1
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%cmp.i = icmp slt i32 %i.inc, 256
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br i1 %cmp.i, label %for.i.header, label %for.n.latch
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for.n.latch:
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%n.inc = add nuw nsw i32 %n, 1
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%cmp.n = icmp slt i32 %n.inc, 100
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br i1 %cmp.n, label %for.n.header, label %exit
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exit:
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ret void
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}
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;; for (int i = 0; i < 256; ++i)
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;; for (int j = 1; j < 256; ++j)
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;; a[j - 1][i] = a[j][255 - i];
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;;
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;; The direction vector of `a` is [* <]. We cannot interchange the loops
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;; because we must handle a `*` dependence conservatively.
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; CHECK: Dependency matrix before interchange:
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; CHECK-NEXT: * <
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; CHECK-NEXT: Processing InnerLoopId = 1 and OuterLoopId = 0
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; CHECK-NEXT: Failed interchange InnerLoopId = 1 and OuterLoopId = 0 due to dependence
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; CHECK-NEXT: Cannot prove legality, not interchanging loops 'for.i.header' and 'for.j'
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define void @all_lt() {
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entry:
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br label %for.i.header
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for.i.header:
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%i = phi i32 [ 0, %entry ], [ %i.inc, %for.i.latch ]
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%i.rev = sub nsw i32 255, %i
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br label %for.j
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for.j:
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%j = phi i32 [ 1, %for.i.header ], [ %j.inc, %for.j ]
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%j.dec = sub nsw i32 %j, 1
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%idx.store = getelementptr inbounds [256 x [256 x float]], ptr @a, i32 0, i32 %j.dec, i32 %i
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%idx.load = getelementptr inbounds [256 x [256 x float]], ptr @a, i32 0, i32 %j, i32 %i.rev
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%0 = load float, ptr %idx.load, align 4
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store float %0, ptr %idx.store, align 4
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%j.inc = add nuw nsw i32 %j, 1
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%cmp.j = icmp slt i32 %j.inc, 256
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br i1 %cmp.j, label %for.j, label %for.i.latch
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for.i.latch:
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%i.inc = add nuw nsw i32 %i, 1
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%cmp.i = icmp slt i32 %i.inc, 256
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br i1 %cmp.i, label %for.i.header, label %exit
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exit:
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ret void
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}
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;; for (int i = 0; i < 255; ++i)
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;; for (int j = 1; j < 256; ++j)
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;; a[j][i] = a[j - 1][i + 1];
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;;
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;; The direciton vector of `a` is [< >]. We cannot interchange the loops
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;; because the read/write order for `a` cannot be changed.
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; CHECK: Dependency matrix before interchange:
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; CHECK-NEXT: < >
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; CHECK-NEXT: Processing InnerLoopId = 1 and OuterLoopId = 0
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; CHECK-NEXT: Failed interchange InnerLoopId = 1 and OuterLoopId = 0 due to dependence
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; CHECK-NEXT: Cannot prove legality, not interchanging loops 'for.i.header' and 'for.j'
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define void @lt_gt() {
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entry:
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br label %for.i.header
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for.i.header:
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%i = phi i32 [ 0, %entry ], [ %i.inc, %for.i.latch ]
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%i.inc = add nuw nsw i32 %i, 1
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br label %for.j
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for.j:
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%j = phi i32 [ 1, %for.i.header ], [ %j.inc, %for.j ]
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%j.dec = sub nsw i32 %j, 1
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%idx.store = getelementptr inbounds [256 x [256 x float]], ptr @a, i32 0, i32 %j, i32 %i
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%idx.load = getelementptr inbounds [256 x [256 x float]], ptr @a, i32 0, i32 %j.dec, i32 %i.inc
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%0 = load float, ptr %idx.load, align 4
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store float %0, ptr %idx.store, align 4
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%j.inc = add nuw nsw i32 %j, 1
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%cmp.j = icmp slt i32 %j.inc, 256
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br i1 %cmp.j, label %for.j, label %for.i.latch
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for.i.latch:
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%cmp.i = icmp slt i32 %i.inc, 255
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br i1 %cmp.i, label %for.i.header, label %exit
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exit:
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ret void
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}
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;; for (int i = 0; i < 20; i++)
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;; for (int j = 0; j < 20; j++)
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;; for (int k = 0; k < 19; k++)
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;; b[i][j][k] = b[i][5][k + 1];
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;;
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;; The direction vector of `b` is [= * *]. We cannot interchange all the loops.
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; CHECK: Dependency matrix before interchange:
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; CHECK-NEXT: = * *
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; CHECK-NEXT: Processing InnerLoopId = 2 and OuterLoopId = 1
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; CHECK-NEXT: Failed interchange InnerLoopId = 2 and OuterLoopId = 1 due to dependence
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; CHECK-NEXT: Cannot prove legality, not interchanging loops 'for.j.header' and 'for.k'
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; CHECK-NEXT: Processing InnerLoopId = 1 and OuterLoopId = 0
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; CHECK-NEXT: Failed interchange InnerLoopId = 1 and OuterLoopId = 0 due to dependence
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; CHECK-NEXT: Cannot prove legality, not interchanging loops 'for.i.header' and 'for.j.header'
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define void @eq_all_lt() {
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entry:
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br label %for.i.header
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for.i.header:
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%i = phi i32 [ 0, %entry ], [ %i.inc, %for.i.latch ]
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br label %for.j.header
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for.j.header:
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%j = phi i32 [ 0, %for.i.header ], [ %j.inc, %for.j.latch ]
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br label %for.k
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for.k:
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%k = phi i32 [ 0, %for.j.header ], [ %k.inc, %for.k ]
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%k.inc = add nuw nsw i32 %k, 1
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%idx.store = getelementptr inbounds [20 x [20 x [20 x i32]]], ptr @b, i32 0, i32 %i, i32 %j, i32 %k
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%idx.load = getelementptr inbounds [20 x [20 x [20 x i32]]], ptr @b, i32 0, i32 %i, i32 5, i32 %k.inc
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%0 = load i32, ptr %idx.load, align 4
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store i32 %0, ptr %idx.store, align 4
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%cmp.k = icmp slt i32 %k.inc, 19
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br i1 %cmp.k, label %for.k, label %for.j.latch
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for.j.latch:
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%j.inc = add nuw nsw i32 %j, 1
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%cmp.j = icmp slt i32 %j.inc, 20
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br i1 %cmp.j, label %for.j.header, label %for.i.latch
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for.i.latch:
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%i.inc = add nuw nsw i32 %i, 1
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%cmp.i = icmp slt i32 %i.inc, 20
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br i1 %cmp.i, label %for.i.header, label %exit
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exit:
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ret void
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}
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