8fdae0c7da
This patch implements the `getAddressComputationCost()` in RISCV TTI which make the gather/scatter with address calculation more expansive that stride cost. Note that the only user of `getAddressComputationCost()` with vector type is in `VPWidenMemoryRecipe::computeCost()`. So this patch make some LV tests changes. I've checked the tests changes in LV and seems those changes can be divided into two groups. * gather/scatter with uniform vector ptr, seems can be optimized to masked.load. * can optimize to stride load/store. ---- After #155739 landed, the assertion (cost mis-aligned) is fixed. I've tested llvm-test-suite w/ rva23u64 and rva23u64_zvl1024b locally and no assertion occurred.
65 lines
2.4 KiB
LLVM
65 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
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; RUN: opt -p loop-vectorize -mtriple riscv64 -mattr=+v < %s -S | FileCheck %s
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; Make sure we don't duplicate the safe divisor cost in the VPlan cost model.
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define void @pr154103(ptr noalias %a, ptr noalias %b, ptr noalias %c, ptr noalias %d) {
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; CHECK-LABEL: define void @pr154103(
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; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], ptr noalias [[D:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[A]], i64 [[IV]]
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; CHECK-NEXT: [[X:%.*]] = load i8, ptr [[GEP]], align 1
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; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[X]] to i64
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 0, [[CONV]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 [[DIV]], 0
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; CHECK-NEXT: br i1 [[CMP]], label %[[THEN:.*]], label %[[LATCH]]
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; CHECK: [[THEN]]:
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; CHECK-NEXT: [[Y:%.*]] = load i8, ptr [[B]], align 1
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[Y]] to i64
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; CHECK-NEXT: [[NOT:%.*]] = xor i64 [[ZEXT]], 0
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; CHECK-NEXT: br label %[[LATCH]]
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; CHECK: [[LATCH]]:
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; CHECK-NEXT: [[COND:%.*]] = phi i64 [ [[NOT]], %[[THEN]] ], [ 0, %[[LOOP]] ]
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; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[COND]] to i16
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; CHECK-NEXT: store i16 [[TRUNC]], ptr [[C]], align 2
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; CHECK-NEXT: store i32 0, ptr [[D]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 7
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; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV]], 0
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; CHECK-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 1, %entry ], [ %iv.next, %latch ]
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%gep = getelementptr i8, ptr %a, i64 %iv
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%x = load i8, ptr %gep, align 1
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%conv = zext i8 %x to i64
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%div = sdiv i64 0, %conv
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%cmp = icmp sgt i64 %div, 0
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br i1 %cmp, label %then, label %latch
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then:
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%y = load i8, ptr %b
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%zext = zext i8 %y to i64
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%not = xor i64 %zext, 0
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br label %latch
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latch:
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%cond = phi i64 [ %not, %then ], [ 0, %loop ]
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%trunc = trunc i64 %cond to i16
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store i16 %trunc, ptr %c
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store i32 0, ptr %d
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%iv.next = add i64 %iv, 7
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%done = icmp eq i64 %iv, 0
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br i1 %done, label %exit, label %loop
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exit:
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ret void
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}
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