3c5b05427d
Pass underlying instruction to getMemoryOpCost in VPReplicateRecipe::computeCost if UsedByLoadStoreAddress is true. Some targets use the underlying instruction to improve costs, and this is needed to match the legacy cost model. Fixes https://github.com/llvm/llvm-project/issues/177780. Fixes https://github.com/llvm/llvm-project/issues/177772.
73 lines
2.3 KiB
LLVM
73 lines
2.3 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt -mtriple=s390x-unknown-linux -mcpu=z13 -passes=loop-vectorize \
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; RUN: -debug-only=loop-vectorize \
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; RUN: -disable-output -enable-interleaved-mem-accesses=false < %s 2>&1 | \
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; RUN: FileCheck %s
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;
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; Check that a scalarized load/store does not get a cost for insterts/
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; extracts, since z13 supports element load/store.
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define void @fun(ptr %data, i64 %n) {
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; CHECK-LABEL: LV: Checking a loop in 'fun'
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; CHECK: LV: Scalarizing: %tmp1 = load i32, ptr %tmp0, align 4
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; CHECK: LV: Scalarizing: store i32 %tmp2, ptr %tmp0, align 4
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; CHECK: Cost of 4 for VF 4: REPLICATE ir<%tmp1> = load ir<%tmp0>
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; CHECK: Cost of 4 for VF 4: REPLICATE store ir<%tmp2>, ir<%tmp0>
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entry:
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br label %for.body
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for.body:
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%i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
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%tmp0 = getelementptr inbounds i32, ptr %data, i64 %i
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%tmp1 = load i32, ptr %tmp0, align 4
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%tmp2 = add i32 %tmp1, 1
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store i32 %tmp2, ptr %tmp0, align 4
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%i.next = add nuw nsw i64 %i, 2
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%cond = icmp slt i64 %i.next, %n
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br i1 %cond, label %for.body, label %for.end
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for.end:
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ret void
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}
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define void @predicated_store(ptr noalias %dst, ptr %src.float, ptr %src.i32.0, ptr %src.i32.1, i64 %n) #0 {
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; CHECK-LABEL: LV: Checking a loop in 'predicated_store'
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; CHECK: Cost of 0 for VF 2: REPLICATE ir<%load.0> = load ir<%gep.0>
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; CHECK: Cost of 0 for VF 2: REPLICATE store ir<0>, ir<%dst>
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; CHECK: Cost of 0 for VF 4: REPLICATE ir<%load.0> = load ir<%gep.0>
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; CHECK: Cost of 0 for VF 4: REPLICATE store ir<0>, ir<%dst>
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ %iv.next, %loop.latch ], [ 0, %entry ]
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%gep.0 = getelementptr i32, ptr %src.i32.0, i64 %iv
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%load.0 = load i32, ptr %gep.0, align 4
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%gep.1 = getelementptr i32, ptr %src.i32.1, i64 %iv
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%ext = sext i32 %load.0 to i64
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%mul = mul i64 %n, %ext
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%gep.float = getelementptr float, ptr %src.float, i64 %mul
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%load.float = load float, ptr %gep.float, align 4
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%fcmp = fcmp ogt float %load.float, 0.000000e+00
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%load.1 = load i32, ptr %gep.1, align 4
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%icmp = icmp sgt i32 %load.1, 0
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%cond = and i1 %fcmp, %icmp
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br i1 %cond, label %if.then, label %loop.latch
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if.then:
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store i32 0, ptr %dst, align 4
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br label %loop.latch
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loop.latch:
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond = icmp eq i64 %iv.next, %n
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br i1 %exitcond, label %exit, label %loop
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exit:
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ret void
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}
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attributes #0 = { "target-cpu" = "z16" }
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