67d0e21a62
This reapplies #171846 with a test case and fix for a legacy cost-model mismatch assertion. In the previous version of the patch, we only considered the plan to contain simplifications when it had a VPBlendRecipe and VF.isScalar() was true. However for some VPlans we may have a blend with only the first lane used: BLEND ir<%phi> = ir<%foo.res> ir<%bar.res>/ir<%c> CLONE ir<%gep> = getelementptr ir<%p>, ir<%phi> vp<%5> = vector-pointer ir<%gep> And in the legacy cost model we cost a blend as a phi if it's uniform: // If we know that this instruction will remain uniform, check the cost of // the scalar version. if (isUniformAfterVectorization(I, VF)) VF = ElementCount::getFixed(1); So this replaces the VF.isScalar() check with vputils::onlyFirstLaneUsed, which matches how the VPlan cost model mirrored the legacy model beforehand. A VPInstruction::Select will also emit a scalar select for a vector VF if only the first lane is used, so this also updates VPBlendRecipe::computeCost to reflect that too.
61 lines
2.2 KiB
LLVM
61 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -p loop-vectorize -S %s | FileCheck %s
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; Test for https://github.com/llvm/llvm-project/issues/111040
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define void @smax_call_uniform(ptr %dst, i64 %x) {
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; CHECK-LABEL: define void @smax_call_uniform(
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; CHECK-SAME: ptr [[DST:%.*]], i64 [[X:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[C:%.*]] = icmp ult i8 -68, -69
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; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i64 [[X]], 0
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; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
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; CHECK: [[LOOP_HEADER]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDEX_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
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; CHECK-NEXT: br i1 [[C]], label %[[LOOP_LATCH]], label %[[ELSE:.*]]
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; CHECK: [[ELSE]]:
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; CHECK-NEXT: [[REM:%.*]] = urem i64 [[MUL]], [[X]]
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; CHECK-NEXT: [[SMAX:%.*]] = tail call i64 @llvm.smax.i64(i64 [[REM]], i64 0)
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; CHECK-NEXT: br label %[[LOOP_LATCH]]
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; CHECK: [[LOOP_LATCH]]:
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; CHECK-NEXT: [[PREDPHI7:%.*]] = phi i64 [ 1, %[[LOOP_HEADER]] ], [ [[SMAX]], %[[ELSE]] ]
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; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[PREDPHI7]], 1
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; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP17]]
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; CHECK-NEXT: store i64 0, ptr [[TMP19]], align 8
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; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
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; CHECK-NEXT: br i1 [[TMP20]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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%c = icmp ult i8 -68, -69
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%mul = mul nsw nuw i64 %x, 0
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br label %loop.header
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loop.header:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
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br i1 %c, label %loop.latch, label %else
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else:
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%rem = urem i64 %mul, %x
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%smax = tail call i64 @llvm.smax.i64(i64 %rem, i64 0)
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br label %loop.latch
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loop.latch:
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%p = phi i64 [ 1, %loop.header ], [ %smax, %else ]
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%add = add i64 %p, 1
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%gep = getelementptr i64, ptr %dst, i64 %add
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store i64 0, ptr %gep, align 8
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%iv.next = add i64 %iv, 1
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%ec = icmp eq i64 %iv.next, 1024
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br i1 %ec, label %exit, label %loop.header
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exit:
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ret void
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}
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declare i64 @llvm.smax.i64(i64, i64)
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