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llvm-project/llvm/test/CodeGen
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Sanjay Patel 7092de4cd2 fix CHECK_NEXT -> CHECK-NEXT 
llvm-svn: 264661
2016-03-28 21:14:24 +00:00
..
AArch64
[AArch64] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize
2016-03-28 18:17:07 +00:00
AMDGPU
CodeGen: Correct specification of PHI nodes
2016-03-28 18:18:41 +00:00
ARM
ARM: maintain BB ordering when expanding WIN__DBZCHK
2016-03-25 19:48:06 +00:00
BPF
BPF: emit an error message for unsupported signed division operation
2016-03-18 22:02:47 +00:00
CPP
…
Generic
Move test/CodeGen/Generic/pr26652.ll to test/CodeGen/X86/pr26652.ll and test it only on X86.
2016-02-25 00:12:18 +00:00
Hexagon
[Hexagon] Improve handling of unaligned vector loads and stores
2016-03-28 15:43:03 +00:00
Inputs
DI: Reverse direction of subprogram -> function edge.
2015-11-05 22:03:56 +00:00
Lanai
[lanai] Add Lanai backend.
2016-03-28 13:09:54 +00:00
Mips
CodeGen: extend RHS when splitting ATOMIC_CMP_SWAP_WITH_SUCCESS.
2016-03-24 15:38:38 +00:00
MIR
MIRParser: Add %subreg.xxx syntax for subregister index operands
2016-03-28 18:18:46 +00:00
MSP430
MSP430InstrInfo::loadRegFromStackSlot forgets to set register def.
2016-02-24 15:15:02 +00:00
NVPTX
[NVPTX] Adds a new address space inference pass.
2016-03-20 20:59:20 +00:00
PowerPC
[PowerPC] On the A2, popcnt[dw] are very slow
2016-03-28 17:52:08 +00:00
SPARC
Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT.
2016-02-26 19:40:34 +00:00
SystemZ
[SystemZ] Avoid LER on z13 due to partial register dependencies
2016-03-14 13:50:03 +00:00
Thumb
Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT.
2016-02-26 19:40:34 +00:00
Thumb2
ARM: Introduce conservative load/store optimization mode
2016-03-02 19:20:00 +00:00
WebAssembly
[WebAssembly] Implement the rotate instructions.
2016-03-22 18:01:49 +00:00
WinEH
[WinEH] Make setjmp work correctly with EH
2016-02-29 19:16:03 +00:00
X86
fix CHECK_NEXT -> CHECK-NEXT
2016-03-28 21:14:24 +00:00
XCore
[MC] Use .p2align instead of .align
2016-01-26 00:03:25 +00:00